A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, a channel structure, and a semiconductor structure. The stack structure includes a plurality of word lines and a select gate line formed on the doped semiconductor layer. The channel structure extends through the plurality of word lines along a first direction and in contact with the doped semiconductor layer. The semiconductor structure extends through the select gate line along the first direction and in contact with the channel structure. The select gate line extends along a second direction perpendicular to the first direction, and the drain select gate line around the semiconductor structure is insulated from the drain select gate line around an adjacent semiconductor structure. A width of the semiconductor structure is less than a width of the channel structure.

A semiconductor storage device includes a stack, a columnar body, and a second conductive layer. The stack includes a plurality of first conductive layers and a plurality of insulating layers. In the stack, the plurality of first conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The second conductive layer is connected to the columnar body. The columnar body includes an insulating core, a memory film, and a semiconductor channel. The memory film is provided between the plurality of first conductive layers and the insulating core. The semiconductor channel is provided between the insulating core and the memory film. An upper surface of the insulating core is located lower than an upper end of the columnar body. The second conductive layer has a main body portion and a protrusion. The protrusion protrudes from the main body portion toward the upper surface of the insulating core, and extends in the first direction within the columnar body. The protrusion is in contact with the semiconductor channel on a bottom surface or a side surface of the protrusion.

A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a stair step structure within the stack structure and having steps comprising lateral edges of the tiers, pillar structures extending through the stack structure and the stair step structure and in contact with a source tier vertically underlying the stack structure, and conductive contact structures in contact with the steps of the staircase structure, the conductive contact structures individually comprising a first portion and a second portion vertically overlying the first portion, the second portion vertically above the pillar structures and having a greater lateral dimension than the first portion. Related microelectronic devices, memory devices, and electronic systems are also described.

A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

A semiconductor device includes a substrate; a first stack structure including first gate electrodes on the substrate; and a second stack structure on the first stack structure; wherein the first stack structure includes a first lower staircase region, a second lower staircase region, and a third lower staircase region, wherein the second stack structure includes a first upper staircase region, a second upper staircase region, a third upper staircase region, and at least one through portion penetrating the second stack structure and on the first to third lower staircase regions, wherein the first lower staircase region has a same shape as a shape of the first upper staircase region, the second lower staircase region has a same shape as a shape of the second upper staircase region, and the third lower staircase region has a same shape as a shape of the third upper staircase region.

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

A microelectronic device comprises a stack structure, contact structures, and additional contact structures. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure is divided into blocks each comprising a stadium structure including steps comprising horizontal ends of the tiers. The contact structures are within a horizontal area of the stadium structure and vertically extend through the stack structure. The additional contact structures are on at least some of the steps of the stadium structure and are coupled to the contact structures. Memory devices and electronic devices are also disclosed.

A semiconductor memory device includes first conductive layers, second conductive layers, a first semiconductor layer, a charge storage layer, and a first wiring. The semiconductor memory device is configured to execute an erase operation including a first and a second erase loop. In the first erase loop, the semiconductor memory device applies a first voltage to at least a part of the first conductive layers and at least a part of the second conductive layers and applies an erase voltage larger than the first voltage to the first wiring. In the second erase loop, the semiconductor memory device applies the first voltage to at least a part of the first conductive layers, applies a second voltage larger than the first voltage to at least apart of the second conductive layers, and applies the erase voltage to the first wiring.

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

An embodiment of a memory device may comprise a vertical channel, a first memory cell formed on the vertical channel, a first wordline coupled to the first memory cell, a second memory cell formed on the vertical channel immediately above the first memory cell, a second wordline coupled to the second memory cell, and an airgap disposed between the first wordline and the second wordline. Other embodiments are disclosed and claimed.