A 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the device includes first redundancy circuits to replace a faulty logic circuit and a second redundancy circuit to replace a faulty memory circuit.

A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; second metal layer overlaying the first metal layer, and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include a High-k metal gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A semiconductor device, the device including: a first single crystal substrate and plurality of logic circuits, where the first single crystal substrate has a device area, where the device area is significantly larger than a reticle size, where the plurality of logic circuits include an array of processors, where the plurality of logic circuits include a first logic circuit, a second logic circuit, and third logic circuit, where the plurality of logic circuits include switching circuits to support replacing the first logic circuit and the second logic circuit by the third logic circuit; and a built-in-test-circuit (“BIST”), where the built-in-test-circuit is connected to test at least the first logic circuit and the second logic circuit.

According to one or more embodiments, a method for manufacturing a semiconductor device includes alternately stacking a first film and a second film on an object to form a multilayer film, then forming a stacked body and a recess by partially removing the multilayer film. A dielectric layer is then formed by applying a composite material to the recess to fill the recess with the dielectric layer. The composite material includes an inorganic material and an organic material. The dielectric layer is then exposed to an oxidizing gas to oxidize the inorganic material and to remove at least part of the organic material from the dielectric layer.

According to one embodiment, a semiconductor storage device includes: a plurality of first wiring layers stacked in a first direction; a first memory pillar including a first semiconductor layer extending in the first direction and penetrating the plurality of first wiring layers; a second wiring layer disposed above the first semiconductor layer; a second semiconductor layer including a first part disposed between the first semiconductor layer and the second wiring layer, a second part extending away from the first semiconductor layer, and a third part provided on the second part; a first insulating layer disposed between the first part and the second wiring layer and between the second part and the second wiring layer; and a second insulating layer provided on the first insulating layer and in contact with at least a portion of the second part.

A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating layer, a second insulating layer, the first insulating layer between the semiconductor substrate and the second insulating layer, a semiconductor layer between the first insulating layer and the second insulating layer, the semiconductor layer extending in a first direction parallel to a surface of the semiconductor substrate, a gate electrode layer extending in a direction perpendicular to the surface; a first insulating film between the semiconductor layer and the gate electrode layer, a second insulating film between the first insulating film and the gate electrode layer the second insulating film in contact with the first insulating layer and the second insulating layer, a polycrystalline silicon region between the first insulating film and the second insulating film; and a metal film between the polycrystalline silicon region and the second insulating film containing titanium and silicon.

A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.

Films that can be useful in large area gap fill applications, such as in the formation of advanced 3D NAND devices, involve processing a semiconductor substrate by depositing on a patterned semiconductor substrate a doped silicon oxide film, the film having a thickness of at least 5 gm, and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. In some embodiments, reflow of the film may occur. The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero as-deposited stress, substantially zero stress shift post-anneal, and substantially zero shrinkage post-anneal.