A thin film transistor array substrate and a method of fabricating the same are disclosed. The thin film transistor array substrate has a device lamination layer, a passivation layer and a pixel electrode layer; the device lamination layer has a substrate, a first signal line layer, a semiconductor layer and a second signal line layer; the passivation layer is formed with a through hole and grooves; the pixel electrode layer is disposed on the passivation layer and inside the grooves; and the pixel electrode layer is connected with the second signal line layer through the through hole. The fabricating cost can be saved and the fabricating efficiency can be improved.

To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. By covering a side surface of an oxide semiconductor layer in which a channel is formed with an oxide semiconductor layer, diffusion of impurities into the inside from the side surface of the oxide semiconductor layer is prevented. By forming a gate electrode in a damascene process, miniaturization and high density of a transistor are achieved. By providing a protective layer covering a gate electrode over the gate electrode, the reliability of the transistor is increased.

The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed between a source/drain metal pattern and a passivation layer located above the source/drain metal pattern, which are formed in a passivation hole area of a non-active area of the array substrate. Accordingly, it may be possible to prevent display failure caused by a delamination phenomenon or peel-off of a material of the passivation layer due to the lack of adhesion strength between a metal layer and the passivation layer in the passivation hole area.

A liquid crystal display with two insulating substrates. A first insulating substrate has crossing signal lines, a pixel electrode, and a drain electrode electrically connected to the pixel electrode through a contact hole. A spacer is formed on the first signal line of the first insulating substrate, and is wider at a first portion close to the first insulating substrate than at a second portion close to the second insulating substrate, and the drain electrode comprises a first portion and a second portion extending in a different direction with respect to the first portion.

The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42). Such a structure further reduces the energy barrier between the drain electrode and the semiconductor layer, making injection of electron easier and ensuring the ON-state current is not lowered down and also helping increase the barrier for transmission of holes, lowering down the leakage current and improving reliability and electrical stability of the TFT.

The TFT array substrate and the manufacturing method thereof are disclosed. The dual-layer structure having the bottom gate electrode, including the metal layer and the transparent metal oxide layer, and the common electrode, including the common electrode, may be formed by the same masking process. In this way, the number of masking processes may be decreased so as to enhance the manufacturing efficiency and the cost.

The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.

A TFT, a method for manufacturing the TFT, and an array substrate are disclosed. In the TFT according to the present disclosure, the nano conductive points that are independent from one another are formed in a channel area of the active layer, so that the channel area of the active layer can be divided into a plurality of sub channels that are independent from one another, and an equivalent electric field strength thereof can be increased. The larger the equivalent electric field strength is, the higher the carrier mobility ratio would be, and the larger the saturation current of the TFT would become. Therefore, the TFT with a higher definition and a higher aperture ratio can be manufactured.

A display substrate includes a first switching element electrically connected to a gate line and that extends in a first direction and electrically connected to a data line that extends in a second direction crossing the first direction, an insulation layer disposed on the first switching element, a shielding electrode disposed on the insulation layer and a pixel electrode that partially overlap the shielding electrode. The shielding electrode includes a first portion that overlaps the data line and extends in the second direction and a second portion that overlaps the gate line and extends in the first direction.

According to one embodiment, a liquid crystal display includes an array substrate provided with pixel electrodes including a first pixel electrode and a second pixel electrode aligning in a first direction, a first gate line placed on one side of the pixel electrodes in a second direction, a second gate line placed on the other side of the pixel electrodes, a source line extending along the second direction, a first pixel switch for switching connection of the source line with the first pixel electrode by a gate signal provided through the first gate line, and a second pixel switch for switching connection of the source line with the second pixel electrode by another gate signal provided through the second gate line, an counter-substrate provided with an common electrode, and a liquid crystal layer held between the substrates.