A thin film transistor array substrate for a display device generally includes: a substrate; a plurality of gate lines and a plurality of data lines arranged on the substrate intersecting with and insulated from each other; and a plurality of pixel elements arranged in areas defined by the gate lines and the data lines. At least one of the pixel elements includes: a switch element; an insulation layer located on the switch element; and a pixel electrode located at the insulation layer. The insulation layers of the pixel elements define a plurality of vias. The pixel electrodes of two adjacent pixel elements are electrically coupled with the corresponding switch elements of the two adjacent pixel elements through a common via defined by the insulation layers of the two adjacent pixel elements. The two adjacent pixel elements are disposed along extensions of the plurality of the gate lines.

A manufacturing method of an array substrate includes: providing a first substrate; forming a gate line, a data line, and a thin-film transistor array on the first substrate; forming a pixel electrode on the thin-film transistor array; depositing and forming a first passivation layer on the pixel electrode, the data line, and the thin-film transistor array; forming a black matrix on the first passivation layer; and forming a common electrode on the black matrix and the first passivation layer. The black matrix has a size that completely covers at least the data line such that when the common electrode is formed on the black matrix and the first passivation layer, a portion of the common electrode that corresponds exactly to the data line is completely spaced from the data line by the black matrix and the first passivation layer.

The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode.

A display device including a substrate having thin film transistors (TFT) comprising: the TFT including an oxide semiconductor film, a gate electrode and an insulating film formed between the oxide semiconductor film and the gate electrode, wherein a first aluminum oxide film and a second aluminum oxide film, which is formed on the first aluminum oxide film, are formed between the insulating film and the gate electrode, an oxygen concentration in the first aluminum oxide film is bigger than an oxygen concentration in the second aluminum oxide film.

An array substrate includes gate lines, data lines and an insulating layer. The data lines all extend in a first direction, and the gate lines all extend in a second direction, the first direction intersecting the second direction. A data line includes first line segments and second line segments that all extend in the first direction and are arranged alternately. The second line segments are disposed at a side of the gate lines proximate to the base, and the first line segments are disposed at a side of the gate lines away from the base. There is no overlap among orthographic projections of the first line segments on the base and orthographic projections of the gate lines on the base. The insulating layer includes first vias. In the first direction, any two adjacent first line segments are electrically connected to a second fine segment through at least two first vias.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

A method of manufacturing a display device, the method including: forming, on a first surface of a substrate, a gate line and a gate electrode; forming a first dielectric layer on the gate line and the gate electrode; forming a data line, a source electrode and a drain electrode on the first dielectric layer; forming a black matrix layer on the first dielectric layer, the data line, the source electrode, and the drain electrode; radiating ultraviolet light on a second surface of the substrate opposing the first surface, the ultraviolet light developing exposed parts of the black matrix layer to form a black matrix pattern; and etching the first dielectric layer using the black matrix pattern as an etching mask to respectively form a first dielectric pattern on the gate line and a gate dielectric pattern on the gate electrode.

A display is disclosed that may prevent a polarizing layer of a display area from being delaminated from a functional panel by absorbing impact caused by an external force by an adhesive enhancement layer arranged outside the polarizing layer on a color filter substrate and an adhesive layer arranged between a non-display area of a transistor substrate and a light emitting portion.

The present disclosure provides an array substrate and a method of manufacturing the same and a display apparatus in which the array substrate is applied. In one embodiment, the method of manufacturing an array substrate at least includes the steps of: forming a first electrode layer, a metal gate layer and a first layer of non-oxide insulation material, the first layer of non-oxide insulation material being formed on an upper surface of the metal gate layer; forming, by using one patterning process, a pattern including a first electrode and a gate such that, after completion of the patterning process, a first non-oxide insulation layer is further formed on the gate and a first sub-electrode belonging to the first electrode layer is further formed below the gate. This method of manufacturing the array substrate is simple, which facilitates mass production of the array substrate as well as the display apparatus.

A liquid crystal display device according to FFS technology is provided, which sufficiently provides a common electrode with common electric potential and improves an aperture ratio of pixels. A pixel electrode is formed of a first layer transparent electrode. A common electrode made of a second layer transparent electrode is formed above the pixel electrode interposing an insulation film between them. The common electrode in an upper layer is provided with a plurality of slits. The common electrode extends over all the pixels in a display region. An end of the common electrode is disposed on a periphery of the display region and connected with a peripheral common electric potential line that provides a common electric potential Vcom. There is provided neither an auxiliary common electrode line nor a pad electrode, both of which are provided in a liquid crystal display device according to a conventional art.