A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional 2D semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as metal fin structure, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide over a substrate; a first conductor and a second conductor being over the oxide and isolated from each other; a third conductor in contact with a top surface of the first conductor; a fourth conductor in contact with a tops surface of the second conductor; a first insulator being over the third conductor and the fourth conductor and having an opening; a second insulator that is positioned in the opening in the first insulator and in contact with the top surface of the first conductor, the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator over the second insulator; and a fifth conductor over the third insulator. The opening in the first insulator overlaps with a region between the third conductor and the fourth conductor. The third insulator is in contact with a top surface of the oxide in a region between the first conductor and the second conductor. A distance between the first conductor and the second conductor is smaller than a distance between the third conductor and the fourth conductor in a cross-sectional view of a transistor in the channel length direction.

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

A semiconductor device structure is provided. The semiconductor device structure includes a stack of channel structures and a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes an etch stop layer extending along a sidewall of the backside conductive contact and a bottom of the gate stack.

A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

A semiconductor device (200) includes an oxide (230) over a substrate: a first conductor (242a1) and a second conductor (242b1) that are over the oxide and separated from each other; a third conductor (242a2) in contact with a part of a top surface of the first conductor; a fourth conductor (242b2) in contact with a part of a top surface of the second conductor; a first insulator (271a, 271b) that is positioned over the third conductor and the fourth conductor and has an opening overlapping with a region between the third conductor and the fourth conductor; a second insulator (255) that is positioned in the opening of the first insulator and in contact with another part of the top surface of the first conductor, another part of the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator (250) that is positioned in the opening of the first insulator and in contact with a top surface of the oxide, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second conductor; and a fifth conductor that is positioned over the third insulator in the opening of the first insulator and includes a region overlapping with the oxide with the third insulator therebetween. A distance (L2) between the first conductor and the second conductor is smaller than a distance (L1) between the third conductor and the fourth conductor.

A display device includes a first transistor including a first light shielding pattern as a first metal layer, a first active layer overlapping the first light shielding pattern, a first gate electrode as a second metal layer, and a first-drain electrode as a third metal layer and connected to the first active layer, a second transistor including a second light shielding pattern spaced apart from the first source and drain electrodes and formed of the third metal layer, a second active layer overlapping the second light shielding pattern, a second gate electrode as a fourth metal layer, and second source and drain electrodes as a fifth metal layer and connected to the second active layer, and a first connection electrode as the third metal layer and connected to the first gate electrode and the first light shielding pattern.

A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.