An IC structure includes a first transistor, a second transistor, a dielectric fin, a dielectric cap, a backside metal structure, and a source/drain contact. The first transistor includes a first channel region, a first gate structure, and first source/drain features disposed on opposite sides of the first gate structure. The second transistor includes a second channel region, a second gate structure, and second source/drain features disposed on opposite sides of the second gate structure. The dielectric fin is disposed between the first and second transistors. The dielectric cap interfaces a backside surface of the dielectric fin. The source/drain contact abuts the dielectric fin and is electrically coupled to a first one of the first source/drain features by way of a silicide layer and electrically coupled to the backside metal rail by way of physical contact established by the source/drain contact and the backside metal rail.

Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.

A thin film transistor comprises: an active layer; and a gate electrode overlapping the active layer, wherein the active layer comprises: a channel portion; a first conductive portion disposed on one side of the channel portion; and a second conductive portion disposed on the other side of the channel portion, wherein the first conductive portion comprises: a first hydrogen conducting portion; and a first connection portion disposed between the first hydrogen conducting portion and the channel portion, and wherein the second conductive portion comprises: a second hydrogen conducting portion; and a second connection portion disposed between the second hydrogen conducting portion and the channel portion, wherein a surface resistance of the first hydrogen conducting portion is greater than a surface resistance of the first connection portion, and a surface resistance of the second hydrogen conducting portion is greater than a surface resistance of the second connection portion.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, a stressor layer is formed in the source/drain space, a metal gate structure including part of the second semiconductor layer as channel regions is formed by a gate replacement process, after the metal gate structure is formed, the stressor layer is at least partially removed, and a source/drain contact comprising metal or a metallic material is formed in the source/drain space from which the stressor layer is at least partially removed.

Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) titanium silicide conductive contact material on the second pEPI region.

The present application discloses a thin film transistor and an array substrate. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode, and at least one of the gate electrode, the source electrode, or the drain electrode is a composite film layer. The composite film layer includes a metal layer, a low reflection functional layer, and an alloy layer which are arranged in layers. The alloy layer covering a surface of the low reflection functional layer can enhance stability of the low reflection functional layer. Because adhesion between the alloy layer and dielectric layers such as silicon oxide, silicon nitride, and silicon oxynitride is stronger than that of the low reflection functional layer, the bulge phenomenon is not easy to occur under a high temperature environment.

An example thin-film transistor includes a source including a body of source material, a drain including a body of drain material, a gate, and a body of semiconductor channel material between the source and the drain. The body of semiconductor channel material includes a metal oxide. The thin-film transistor further includes a source-channel interface between the body of source material and the body of semiconductor channel material. The source-channel interface includes a nitrogen-containing metal oxide. A similar or identical drain-channel interface may be provided. The nitrogen-containing metal oxide may be formed using plasma.

A semiconductor device that occupies a small area is provided. The semiconductor device includes an oxide semiconductor layer, first to third conductive layers, a first insulating layer, and a second insulating layer. The first conductive layer includes a first metal layer and a first metal oxide layer including the same metal as each other. The first metal layer is electrically connected to the oxide semiconductor layer through the first metal oxide layer. The second conductive layer includes a second metal layer and a second metal oxide layer including the same metal as each other. The second metal layer is electrically connected to the oxide semiconductor layer through the second metal oxide layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first insulating layer. The oxide semiconductor layer is in contact with the top surface of the first metal oxide layer, the top surface and a side surface of the second metal oxide layer, and a side surface of the first insulating layer. The second insulating layer is positioned over the oxide semiconductor layer. The third conductive layer is positioned over the second insulating layer and overlaps with the oxide semiconductor layer with the second insulating layer therebetween.

The present disclosure relates to a display panel, a display device, and a method for manufacturing a display panel. The display panel includes a display area, an aperture area, and an inner non-display area between the display area and the aperture area. The display area is arranged with an electroluminescent device. The electroluminescent device includes a common layer extending to the inner non-display area. The inner non-display area is arranged with a partition bar at least partially surrounding the aperture area. The common layer located in the inner non-display area is partitioned by the partition bar.