A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

A thin film transistor includes a substrate, a gate electrode formed on the substrate, an insulation layer covering the gate electrode, source/drain electrodes, which are formed horizontally spaced apart on the insulation layer and comprise a conductive metal pattern and a conductive oxide layer covering the conductive metal pattern, a semiconductor layer bonded to the spaced apart space of the source/drain electrodes, and a passivation layer covering the source/drain electrodes and the semiconductor layer.

Backside source or drain contact selectivity using colored hardmasks is described. A structure includes a first epitaxial source or drain structure at an end of first nanowires or a fin, a first conductive source or drain contact vertically beneath a bottom of the first epitaxial source or drain structure, and a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of second nanowires or a fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and with a second hardmask material beneath the second conductive source or drain contact. The first hardmask material extends laterally beyond the first conductive source or drain contact and is continuous laterally around the second hardmask material.

The present disclosure relates to a ferroelectric thin film transistor and may include: a substrate; a gate electrode layer formed on the substrate; a ferroelectric layer formed on the gate electrode layer, including a hafnium-based oxide, and including an uneven portion having at least one or more step that is formed on the gate electrode layer; a semiconductor channel layer formed on the ferroelectric layer and including an oxide semiconductor; a drain electrode layer connected to the semiconductor channel layer at one side of the gate electrode layer; and a source electrode layer connected to the semiconductor channel layer at the other side of the gate electrode layer.

A method for fabricating single silicon carbide nanowires includes synthesizing silicon carbide using chemical vapor deposition; adding the silicone carbide to a solvent to form a suspension, sonicating the suspension, and separating a plurality of silicon carbide nanowires from the suspension after sonicating the suspension. Implementations of the method for fabricating single silicon carbide nanowires includes where synthesizing silicon carbide using chemical vapor deposition may include the introduction of silicon vapor, or adjusting a pH or maintaining a constant volume during the solution process. A bottom-gate transistor, or other integrated circuits may include layers having one or more of a plurality of silicon carbide nanowires positioned between the source and the drain.

In a thin-film transistor device, an inorganic insulating layer covers the via wall of a via, an active layer is disposed on a first electrode, the inorganic insulating layer, and a second electrode, a gate insulating layer covers the active layer, and a gate is disposed on a side of the gate insulating layer away from the via wall of the via, where the first electrode, the second electrode, and the inorganic insulating layer have the same conductive element.

A semiconductor device structure is provided. The semiconductor device structure includes a channel structure and a first epitaxial structure and a second epitaxial structure beside opposite sides of the channel structure. The semiconductor device structure also includes a gate stack over the channel structure and a backside conductive structure electrically connected to the second epitaxial structure. A top of the second epitaxial structure is between a top of the backside conductive structure and a top of the gate stack. The semiconductor device structure further includes a dielectric layer extending along a sidewall of the backside conductive structure and extending beyond opposite sidewalls of the gate stack.

A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a semiconductor device comprises a semiconductor channel, a source region adjacent to the semiconductor channel, and a drain region adjacent to the semiconductor channel. In an embodiment, the source region and the drain region each comprise a trench, a conformal silicide lining the trench, and a binary metallic alloy filling the trench.

A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.