A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.

A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

A COA substrate is provided including a substrate base, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a color resist layer, and a pixel electrode layer. The surface of the color resist layer is provided with a protrusion and a recess, and the pixel electrode is disposed on the protrusion and the recess. A plurality of protrusions and a plurality of recesses are provided, thereby increasing the display quality of a liquid crystal display device.

A display panel and a display device including the display panel are provided. The display panel includes data lines and scan lines arranged to be intersected, and a sensing antenna. The data lines and the scan lines are located in a display region of the display panel, and define multiple sub-pixels. The sensing antenna includes multiple sensing coils and is at least partly located in the display region of the display panel, and projections of the data lines and/or the scan lines cover projections of the sensing coils in a direction perpendicular to a surface of the display panel, in order to avoid affection on an aperture ratio of the display panel caused by the sensing coils located in the display region.

In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

The present invention provides a TFT substrate structure and a manufacturing method thereof. A metal oxide semiconductor layer is formed on an amorphous silicon layer to replace an N-type heavily-doped layer. The potential barrier between the amorphous silicon layer and metal layer is relatively low, making it possible to form an ohmic contact and thus increasing current efficiency, without the need of doping other ions to form the N-type heavily-doped layer. Further, the metal oxide semiconductor layer comprises numerous defects that trap holes so that during the operation of the TFT, even a great negative voltage is applied to the gate terminal to thus form a hole conducting channel, the holes may hardly move from the source/drain terminals through the metal oxide semiconductor layer and the semiconductor layer to reach the conducting channel and consequently, the current leakage issue occurring in a hole conducting zone of a conventional TFT substrate structure can be improved and severe bending of the hole current curve and poor reliability are also improved.

A display device includes: a first substrate; a gate electrode on the first substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a first passivation layer including a silicon nitride-based material and on the semiconductor layer, the source electrode, and the drain electrode; a second passivation layer including a silicon nitride-based material and on the first passivation layer; and a third passivation layer including a silicon nitride-based material and on the second passivation layer, where a content ratio of silicon in the first passivation layer is higher than a content ratio of silicon in the second passivation layer, and the content ratio of silicon in the second passivation layer is higher than a content ratio of silicon in the third passivation layer.

An object of the invention is to improve the reliability of a light-emitting device. Another object of the invention is to provide flexibility to a light-emitting device having a thin film transistor using an oxide semiconductor film. A light-emitting device has, over one flexible substrate, a driving circuit portion including a thin film transistor for a driving circuit and a pixel portion including a thin film transistor for a pixel. The thin film transistor for a driving circuit and the thin film transistor for a pixel are inverted staggered thin film transistors including an oxide semiconductor layer which is in contact with a part of an oxide insulating layer.

A manufacturing method of a thin film transistor comprises: sequentially forming a pattern of gate, a gate insulation layer film, an active layer film and an ohmic contact layer film, a first etching resist module within a channel region to be formed, and a source and drain metallic layer film on a substrate; forming a pattern comprising the source and drain by wet etching process by shielding the active layer film and the ohmic contact layer film positioned within the channel region to be formed, by use of the first etching resist module; and forming a pattern comprising the ohmic contact layer and the active layer by dry etching process. A thin film transistor, an array substrate comprising the thin film transistor and a display device comprising the array substrate are also disclosed.