The present invention provides a TFT substrate structure and a manufacturing method thereof. The TFT substrate structure of the present invention includes an N-type lightly-doped amorphous silicon layer and an N-type heavily-doped amorphous silicon layer arranged between an amorphous silicon layer and a metal layer to form a gradient of doping concentration so as to reduce the potential barrier between the metal layer and the amorphous silicon layer, making injection of electrons easy and reducing the leakage current without lowering an operation current, thereby improving the electrical property of the TFT. The manufacturing method of a TFT substrate structure of the present invention includes forming an N-type lightly-doped amorphous silicon layer and an N-type heavily-doped amorphous silicon layer between an amorphous silicon layer and a metal layer to effectively reduce the potential barrier between the metal layer and the amorphous silicon layer, making injection of electrons easy and reducing the leakage current without lowering an operation current, thereby improving the electrical property of the TFT.

Embodiments of the invention provide a display panel and a manufacturing method thereof, and a display device comprising such a display panel. At least one sensor is integrated into the display panel through a semiconductor process that is at least partially synchronously performed with processes of forming the array substrate and/or color filter substrate of the display panel, such that an integration level of the sensor on the display panel is increased and the process is simplified.

The present invention provides a TFT substrate structure and a manufacturing method thereof. A metal oxide semiconductor layer is formed on an amorphous silicon layer to replace an N-type heavily-doped layer. The potential barrier between the amorphous silicon layer and metal layer is relatively low, making it possible to form an ohmic contact and thus increasing current efficiency, without the need of doping other ions to form the N-type heavily-doped layer. Further, the metal oxide semiconductor layer comprises numerous defects that trap holes so that during the operation of the TFT, even a great negative voltage is applied to the gate terminal to thus form a hole conducting channel, the holes may hardly move from the source/drain terminals through the metal oxide semiconductor layer and the semiconductor layer to reach the conducting channel and consequently, the current leakage issue occurring in a hole conducting zone of a conventional TFT substrate structure can be improved and severe bending of the hole current curve and poor reliability are also improved.

There is provided a repair technique capable of repairing interconnect lines and the like in an electronic device with ease and with reliability and capable of suppressing the increase in the number of manufacturing steps associated with the repair to suppress the increase in manufacturing costs. The electronic device having a multi-layer interconnection structure includes: a foundation layer; a patterned interconnect line provided on the foundation layer; and an insulation film formed on the foundation layer and the interconnect line. The insulation film includes at least one thin film part in which at least part of the insulation film which lies on the interconnect line has a thickness less than that of its surroundings.

The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.

An array substrate, a display device and a manufacturing method of the array substrate. The array substrate includes: a base substrate (1) and a plurality of pixel units located on the base substrate (1), each of the pixel units including a thin film transistor unit. The thin film transistor unit includes: a gate electrode located on the base substrate (1), a gate insulating layer (3) located on the gate electrode, an active layer (4) located on the gate insulating layer (3) and opposed to the gate electrode in position, an ohmic layer (5) located on the active layer (4), a source electrode (6a) and a drain electrode (6b) that are located on the ohmic layer (5) and a resin passivation layer (8) that are located on the source electrode (6a) and the drain electrode (6b) and covers the substrate.

According to one embodiment, a liquid crystal display includes an array substrate provided with pixel electrodes including a first pixel electrode and a second pixel electrode aligning in a first direction, a first gate line placed on one side of the pixel electrodes in a second direction, a second gate line placed on the other side of the pixel electrodes, a source line extending along the second direction, a first pixel switch for switching connection of the source line with the first pixel electrode by a gate signal provided through the first gate line, and a second pixel switch for switching connection of the source line with the second pixel electrode by another gate signal provided through the second gate line, an counter-substrate provided with an common electrode, and a liquid crystal layer held between the substrates.

A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.

A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and including a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode, a first electrode disposed on the gate insulating layer, a first passivation layer disposed on the first electrode and including silicon nitride, a second passivation layer disposed on the first passivation and including silicon nitride, and a second electrode disposed on the passivation layer, in which a first ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the first passivation layer is different from a second ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the second passivation layer.

A display device includes a substrate, a plurality of pixels above the substrate, each of the pixels including a light emitting element, a display region including the plurality of pixels, a thin film transistor which each of the plurality of pixels includes, a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element, a sealing film including a second inorganic insulating material and covering the light emitting element, and at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film, wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.