According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a film to be processed on a substrate. The method includes forming a first resist pattern on the film, the first resist pattern having a first stepped structure including a plurality of steps. The method includes forming a second resist pattern on the first resist pattern by use of a template for nanoimprint. The second resist pattern has a second stepped structure, which is arranged corresponding to the first stepped structure and is formed such that a step-up surface extends perpendicularly to a flat surface. The method includes processing the film through the second resist pattern and the first resist pattern.

According to one embodiment, a semiconductor memory device includes a first transistor which includes a first end coupled to a first node, a second end, and a gate coupled to the second end. A second transistor includes a third end coupled to the first node, a fourth end, and a gate coupled to the fourth end. A third transistor is provided between a first bit line and a second node in a first sense amplifier. A selector is configured to supply a gate of the third transistor with one of a potential of the second end and a potential of the fourth end.

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar section and an interconnection section. The stacked body includes a first insulating layer, a first electrode layer, a second insulating layer, and a second electrode layer. The first insulating layer includes a first surface facing the substrate, and a second surface facing the first electrode layer and opposite to the first surface. The second insulating layer includes a third surface facing the first electrode layer, and a fourth surface facing the second electrode layer and opposite to the third surface. A width of the interconnection section located between the first surface and the second surface in a second direction perpendicular to a stacking direction and a first direction is larger than a width of the interconnection section located between the third surface and the fourth surface in the second direction.

According to the embodiment, the semiconductor device includes: a stacked body; first interconnect and a second interconnect; a first columnar portion, a second columnar portion, a third columnar portion, and a fourth columnar portion; a first intermediate interconnect; a first connection portion; a second connection portion; and a second intermediate interconnect. The stacked body includes a plurality of electrode layers. The first interconnect and the second interconnect are provided on the stacked body, and extend in a first direction crossing a stacking direction of the stacked body. The first intermediate interconnect is electrically connected to the first interconnect, the first columnar portion, and the second columnar portion. The second intermediate interconnect is provided at a height different from a height of the first intermediate interconnect, and is electrically connected to the second interconnect, the third columnar portion, and the fourth columnar portion.

A semiconductor memory device includes a semiconductor layer, a stacked body on the semiconductor layer, the stacked body including a first insulating layer and an electrode layer, a channel layer within and extending through the stacked body and electrically connected to the semiconductor layer, a second insulating layer between the channel layer and the electrode layer, a charge storage layer between the second insulating layer and the electrode layer, and a third insulating layer between the charge storage layer and the electrode layer. The third insulating layer includes an insulating film on a side of the charge storage layer and a first dielectric layer on a side of the electrode layer. The first dielectric layer includes a first material, a second material, and oxygen. The first material has a dielectric constant higher than a dielectric constant of aluminum oxide when the first material is converted into an oxide, and an oxide of the second material has a dielectric constant lower than the dielectric constant of the oxide of the first material.

A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.

According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.

According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction.