A heterojunction bipolar transistor (HBT) amplifier device includes transistor fingers arranged in parallel on a substrate. Each transistor finger includes a base/collector mesa stripe shaving a trapezoidal shaped cross-section with sloping sides, and having a base stacked on a collector; a set of emitter mesa stripes arranged on the base/collector mesa stripe; and emitter metallization formed over the set of emitter mesa stripes and the base/collector mesa. The emitter metallization includes a center portion for providing electrical and thermal connectivity to the emitter mesa stripes and extended portions extending beyond the base and overlapping onto the sloping sides of the base/collector mesa stripe for increasing thermal coupling to the collector. A common conductive pillar is formed over the transistor fingers for providing electrical and thermal conductivity. Also, thermal shunts are disposed on the substrate between adjacent transistor fingers, where the thermal shunts are electrically isolated from the transistor fingers.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

A Ga.sub.2O.sub.3 heterojunction bipolar device includes a first electrode, a second electrode, a -Ga.sub.2O.sub.3 substrate between the first electrode and the second electrode, and a NiO.sub.x layer in contact with (201), (001), or (010) plane of the -Ga.sub.2O.sub.3 substrate. A surface of the -Ga.sub.2O.sub.3 substrate defines a (201), (001), or (010) plane, and the interface between the NiO.sub.x layer and the -Ga.sub.2O.sub.3 substrate is a p-n heterojunction. Fabricating the Ga.sub.2O.sub.3 heterojunction bipolar device includes depositing a first electrode on a surface of a Ga.sub.2O.sub.3 substrate defining a (201), (001), or (010) plane of the -Ga.sub.2O.sub.3 substrate, depositing a NiO.sub.x layer on an opposite surface of the substrate, and depositing a second electrode on the NiO.sub.x layer to yield the device.

A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

A bipolar transistor and a method of making a bipolar transistor. The method includes providing a semiconductor substrate having a major surface, one or more layers located beneath the major surface for forming an intrinsic base, and a collector. The method also includes depositing a first oxide layer on the major surface, depositing a second oxide layer on the first oxide layer, and depositing an extrinsic base layer on the second oxide layer. The method further includes forming an emitter window through the extrinsic base layer. The method also includes removing at least a part of the second oxide layer to form a first cavity and forming an initial part of a base link region in the first cavity. The method also includes removing at least a part of the first oxide layer to form a second cavity and filling the second cavity to form a completed base link region.

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a collector; a base region above the collector; an emitter laterally connecting to the base region; and an extrinsic base connecting to the base region.

A process for making a transistor that includes removing a sacrificial material under a base layer that includes dopants for an intrinsic base of a transistor. After the removal of the sacrificial layer to form a cavity directly under the base layer, a semiconductor material is formed in the cavity. The semiconductor layer includes dopants for a current electrode of the transistor that is located directly under the intrinsic base of the transistor.

A bipolar junction transistor has a collector over a substrate, a base over the collector, and an emitter over the base. The base includes a III-V ternary semiconductor alloy including first, second, and third elements, and having a narrower bandgap than a binary semiconductor alloy including only the first and second elements. At least a portion of the base has a differential concentration of the third element such that a concentration of the third element at a first location in the base is greater than at a second location in the base, the second location between the first location and the collector.

A bipolar junction transistor a base over a collector, the base including a III-V ternary semiconductor alloy including first, second, and third elements. The LI-V ternary semiconductor alloy has a narrower bandgap than a binary semiconductor alloy including only the first and second elements. A ledge between an emitter and a base contact being 0.5 m or less.

A bipolar junction transistor has a collector over a substrate and a base structure over the collector, the base including a III-V ternary semiconductor alloy, the base having a base contact formed thereon. An emitter is over the base structure, and a ledge between the emitter structure and the base contact is 0.3 m or less.