A nitride semiconductor device includes a first nitride semiconductor layer that constitutes an electron transit layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, and a gate portion that is formed on the second nitride semiconductor layer. The gate portion includes a first semiconductor gate layer of a ridge shape that is disposed on the second nitride semiconductor layer and is constituted of a nitride semiconductor containing an acceptor type impurity, a second semiconductor gate layer that is formed on the first semiconductor gate layer and is constituted of a nitride semiconductor with a larger bandgap than the first semiconductor gate layer, and a gate electrode that is formed on the second semiconductor gate layer and is in Schottky junction with the second semiconductor gate layer.

A semiconductor device includes a substrate, a source electrode extending, a drain electrode, a first gate electrode extending in a first direction and provided between the source electrode and the drain electrode, a second gate electrode extending in the first direction and provided on the substrate in the first direction of the first gate electrode between the source electrode and the drain electrode, a gate pad provided so as to interpose the first gate electrode between the second gate electrode and the gate pad and electrically connected to the first gate electrode, a gate wiring provided above the source electrode and electrically connecting the gate pad and the second gate electrode, and a guard metal layer provided between the gate wiring and the drain electrode, at least a part of the guard metal layer being provided above the source electrode and electrically connected to the source electrode.

A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

A nitride semiconductor device 1 includes a first nitride semiconductor layer that constitutes an electron transit layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, a gate portion that is formed on the second nitride semiconductor layer, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are opposingly disposed across the gate portion. The gate portion includes a third nitride semiconductor layer of a ridge shape that is formed on the second nitride semiconductor layer and contains an acceptor type impurity and a gate electrode that is formed on the third nitride semiconductor layer. A film thickness of the third nitride semiconductor layer is greater than 100 nm.

A gallium nitride-based semiconductor device includes an amorphous glass substrate having a first surface and a second surface opposite to the first surface; a gallium nitride-based semiconductor layer on the first surface of the amorphous glass substrate, and a compensation layer on the second surface of the amorphous glass substrate. A thermal expansion coefficient of the compensation layer is more than a thermal expansion coefficient of the amorphous glass substrate and less than a thermal expansion coefficient of the gallium nitride-based semiconductor layer.

A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.

A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.

Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.