A semiconductor device including a HEMT using an N polar plane has a semiconductor laminated structure including a base layer, a barrier layer, and a channel layer. The base layer has a first surface, which is a (000-1) plane, and contains AlN. The barrier layer is formed on the first surface side of the base layer where the first surface is provided, contains AlGaN, and is lattice-relaxed with respect to the base layer. The channel layer is formed on a second surface side of the barrier layer and contains GaN. The barrier layer is not lattice-matched with but is lattice-relaxed with respect to the base layer, and the channel layer is lattice-matched with the barrier layer.

A semiconductor device includes a substrate, a back-barrier layer, a channel layer that has a band gap smaller than a band gap of the back-barrier layer, a first barrier layer that has a band gap larger than the band gap of the channel layer, a second barrier layer that is provided to fill a first recessed portion and has a band gap larger than the band gap of the channel layer, a source electrode, a drain electrode, and a gate electrode. An In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer. An Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layer.

An epitaxial layer (2) is formed on a substrate (1). A field effect transistor (3) is formed on the epitaxial layer (2). A drain pad (8) is formed on the epitaxial layer (2). The drain pad (8) is connected to a drain electrode (5) of the field effect transistor (3). A back surface electrode (13) is formed on a back surface of the substrate (1) and connected to a source electrode (6) of the field effect transistor (3). A wire (16) is bonded to the drain pad (8). A cavity (17) is formed in the substrate (1) directly below the drain pad (8). The cavity (17) is not formed directly below a bonding portion of the wire (16).

Semiconductor devices and associated fabrication methods are disclosed. In one disclosed approach a process for forming a semiconductor device is provided. The process includes: implanting a first region of semiconductor material using a first channeled implant with a first conductivity type; and implanting, after the first channeled implant, a second region of semiconductor material using a second channeled implant with a second conductivity type. The first channeled implant disrupts a crystal structure of the first region of semiconductor material and does not disrupt a crystal structure of the second region of semiconductor material.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

This semiconductor device includes a substrate, a channel layer provided on one side of a surface of the substrate and including a first nitride semiconductor having a first bandgap, a barrier layer provided on an opposite side of the channel layer from the substrate and including a second nitride semiconductor that includes Al.sub.x1In.sub.y1Ga.sub.(1x1y1)N (0<x1<1, 0<y1<1) and has a second bandgap larger than the first bandgap of the first nitride semiconductor, and an intermediate layer provided in the barrier layer and including a third nitride semiconductor that includes Al.sub.x2In.sub.y2Ga.sub.(1x2y2)N (0x2<1, 0y2<1), and the semiconductor device satisfies (1x1y1)<(1x2y2).

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

An epitaxial wafer 1 includes a Ga.sub.2O.sub.3-based substrate, a metal layer, and a -Ga.sub.2O.sub.3 layer. The Ga.sub.2O.sub.3-based substrate has a first principal surface and a second principal surface opposite from the first principal surface. The metal layer is formed on the first principal surface of the Ga.sub.2O.sub.3-based substrate. The metal layer has a plurality of openings. The -Ga.sub.2O.sub.3 layer covers the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer. The metal layer is made of a material such as a noble metal or a refractory metal. The thickness of the -Ga.sub.2O.sub.3 layer is smaller than the thickness of the Ga.sub.2O.sub.3-based substrate.

An epitaxial wafer 1 includes a Ga.sub.2O.sub.3-based substrate, a metal layer, and a -Ga.sub.2O.sub.3 layer. The Ga.sub.2O.sub.3-based substrate has a first principal surface and a second principal surface opposite from the first principal surface. The metal layer is formed on the first principal surface of the Ga.sub.2O.sub.3-based substrate. The metal layer has a plurality of openings. The -Ga.sub.2O.sub.3 layer covers the first principal surface of the Ga.sub.2O.sub.3-based substrate and the metal layer. The metal layer is made of a material such as a noble metal or a refractory metal. The thickness of the -Ga.sub.2O.sub.3 layer is smaller than the thickness of the Ga.sub.2O.sub.3-based substrate.