A method comprises forming a first gate of a first field effect transistor (FET) device over a first channel region of a first fin arranged on a substrate, forming a second gate of a second FET device over a second channel region of a second fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region, etching to remove portions of the insulator material and define a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device, and depositing a conductive material in the first cavity to define a first contact and depositing a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact.

A semiconductor wafer includes a base wafer, a first semiconductor portion that is formed on the base wafer and includes a first channel layer containing a majority carrier of a first conductivity type, a separation layer that is formed over the first semiconductor portion and contains an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion, and a second semiconductor portion that is formed over the separation layer and includes a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type.

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.

A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

A semiconductor device that includes at least one not intentionally doped compositionally graded ternary, quaternary, quinary or senary ultra-wide bandgap alloy layer. Composition grading along a predetermined axis and changes in energy bandgap in space by compositional grading, alloy material, and effects of said any adjacent layers results in the at least one not intentionally doped compositionally graded ternary, quaternary, quinary or senary ultra-wide bandgap alloy layer being one of an n-type layer with a density distribution of electrons or a p-type layer with a density distribution of holes, depending on design choices. The at least one not intentionally doped compositionally graded ternary, quaternary, quinary or senary ultra-wide bandgap alloy layer is disposed on a substrate layer.

A nitride semiconductor device includes: a substrate; a drift layer, a high-resistance layer, and a first base layer above the substrate in stated order; a gate opening penetrating through the first base layer and the high-resistance layer to the drift layer; an electron transport layer and an electron supply layer covering an upper portion of the first base layer and the gate opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; an electrode opening penetrating through the electron supply layer and the electron transport layer to the first base layer; a potential fixing electrode in contact with the first base layer at a bottom part of the electrode opening; and a drain electrode below the substrate.