A method for fabricating a display panel includes: forming a plurality of N-type doped amorphous silicon structures on a substrate; forming an amorphous silicon layer covering the N-type doped amorphous silicon structures and the substrate; blue laser annealing the amorphous silicon layer and the N-type doped amorphous silicon structures, so that the N-type doped amorphous silicon structures are converted into N-type heavily doped polysilicon structures, a part of the amorphous silicon layer in contact with one of the N-type doped amorphous silicon structures and located between two adjacent N-type doped amorphous silicon structures is converted into an N-type lightly doped polysilicon structure, and other parts of the amorphous silicon layer are converted into a polysilicon layer; and patterning the polysilicon layer to form a semiconductor layer.

A semiconductor device that occupies a small area is provided. The semiconductor device includes a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer over the second conductive layer, a semiconductor layer and a third conductive layer over the first insulating layer, a second insulating layer over the semiconductor layer and the third conductive layer, and a fourth conductive layer over the second insulating layer; at least part of the second conductive layer is in contact with a top surface of the first conductive layer; the semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second conductive layer, the third conductive layer, and a side surface of the first insulating layer; and the fourth conductive layer overlaps with the semiconductor layer with the second insulating layer therebetween.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.

A display apparatus can include a first thin film transistor including a first active layer including polycrystalline silicon, a first gate electrode overlapping the first active layer with a first gate insulation layer therebetween, and a first source electrode and a first drain electrode connected to the first active layer, a first interlayer insulation layer disposed on the first gate electrode, a second thin film transistor including a second active layer including an oxide semiconductor, a second gate electrode overlapping the second active layer with a second gate insulation layer therebetween, and a second source electrode and a second drain electrode connected to the second active layer, and a second interlayer insulation layer disposed on the first gate electrode, the second gate electrode, and the second gate insulation layer. Also, the second gate insulation layer and the second interlayer insulation layer comprise a dopant for doping the second active layer.

A thin film transistor and a preparation method therefor, a memory, and a display. The thin film transistor comprises: a first source/drain layer (1), a first insulating layer (2), a second source/drain layer (3) and a second insulating layer (4) which are sequentially stacked; and a gate (6) and a channel layer (5) surrounding the gate (6), which are located in the second insulating layer (4), the second source/drain layer (3) and the first insulating layer (2). The channel layer (5) is in contact with the first source/drain layer (1), the first insulating layer (2), the second source/drain layer (3) and the second insulating layer (4). The thin film transistor is a CAA architecture of an annular channel surrounding the gate (6). Moreover, the leakage current of the gate (6) and the parasitic capacitance of the thin film transistor can be reduced by adding the second insulating layer (4) above the second source/drain layer (3).

Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece having a channel region, a gate structure over the channel region, gate spacers extending along sidewalls of the gate structure, and an etch stop layer extending along sidewalls of the gate spacers. The method also includes performing an etching process to recess the gate spacers and the gate structure, thereby forming a funnel-shaped trench, depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench, etching back the dielectric layer to form dielectric spacers on the recessed gate spacers, forming a metal cap on the gate structure without forming the metal cap on the recessed gate spacers, and forming a dielectric cap on the metal cap.

An example thin-film transistor includes a source and a gate. The source includes a body of source metal and a body of capacitance-tuning material disposed on the body of source metal. The body of capacitance-tuning material is configured to control a capacitance between the source and the gate. A drain of the thin-film transistor may also include a body of capacitance-tuning material. Capacitance-tuning material may be provided outside the source/drain, for example, adjacent a gate dielectric material. The thin-film transistor may further include a body of reducing material to draw oxygen out of other materials of the thin-film transistor. The thin-film transistor may further include a body of hardmask material used during the making of the thin-film transistor.

To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

Disclosed in the present disclosure are a transistor device and a memory. The transistor device comprises: a gate; a semiconductor channel, which surrounds a surface of the gate, wherein the semiconductor channel comprises a multi-layer thin film structure, and the multi-layer thin film structure comprises an indium oxide thin film layer, a gallium oxide thin film layer and a zinc oxide thin film layer; a first source drain, which is disposed at a first end of the semiconductor channel; and a second source drain, which is disposed at a second end of the semiconductor channel. By means of the present disclosure, the control ability of the turn-off of the semiconductor channel and the mobility of the semiconductor channel can be adjusted and balanced.

To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/m or less and off-state current at 85 C. can be 100 aA/m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85 C. can be 100 aA/m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.