Provided on a substrate are an N.sup.+ layer connecting to a source line SL and an N.sup.+ layer connecting to a bit line BL that are located at opposite ends of a Si pillar standing in an upright position along the vertical direction, an N layer continuous with the N.sup.+ layer, an N layer continuous with the N.sup.+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connecting to a plate line PL, and a second gate conductor layer surrounding a second gate insulating layer surrounding the Si pillar and connecting to a word line WL. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data retention operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region of the Si pillar, and a data erase operation for removing the holes from the channel region.

There are provided the steps of forming an N.sup.+ layer 21a and a Si pillar 26 on a substrate 20, the N.sup.+ layer 21a being connected to a source line SL, the Si pillar 26 standing in a vertical direction and being composed of a P.sup.+ layer 22a in a center portion thereof and a P layer 25a surrounding the P.sup.+ layer 22a; forming an N.sup.+ layer 3b and HfO.sub.2 layers 28a and 28b of gate insulating layers on the P.sup.+ layer 22a, the N.sup.+ layer 3b being connected to a bit line BL, the HfO.sub.2 layers 28a and 28b surrounding the Si pillar 26; and forming a TiN layer 30a of a gate conductor layer and a TiN layer 30b of a gate conductor layer, the TiN layer 30a surrounding the HfO.sub.2 layer 28a and being connected to a plate line PL, the TiN layer 30b surrounding the HfO.sub.2 layer 28b and being connected to a word line WL. Voltages to be applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data write operation for holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in the Si pillar 26 and a data erase operation for discharging the hole group from within the Si pillar 26.

An N.sup.+ layer 21 connected to a source line SL on a substrate 20 has thereon first Si pillars 22aa to 22da. The Si pillars 22aa to 22da are surrounded, and Lg1 between opposing intersections among intersections between a line X-X′ and outer peripheral edges of HfO.sub.2 layers 24a serving as gate insulating layers surrounding the Si pillars 22aa and 22ba is larger than a thickness Lg2 of the HfO.sub.2 layers 24a crossing a line Y-Y′ and is smaller than twice the thickness Lg2. Further, TiN layers 25aa and 25ba are connected to plate lines PL1a and PL1br, and TiN layers 25ab and 25bb are connected to plate lines PL2a and PL2b, the TiN layers 25aa and 25ba and the TiN layers 25ab and 25bb surrounding the HfO.sub.2 layers 24a, extending in the line X-X′ direction, and being separated from each other. Further, TiN layers 27a and 27b surround Si pillars 22ab to 22db respectively positioned on the Si pillars 22aa to 22da and are connected to word lines WL1 and WL2, and metal wiring layers 32a and 32b are connected to N.sup.+ layers 28a to 28d positioned on the Si pillars 22ab to 22db and are connected to bit lines BL1 and BL2. As a result, a dynamic flash memory cell is formed.

A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page sum-of-products read operation, a voltage is applied to the driving control line such that memory cell currents, in the group of memory cells, flowing into the bit lines multiply N-fold (N is a positive integer).

In a memory device, pages are arrayed in a column direction on a substrate, each page constituted by memory cells arrayed in row direction on a substrate. Each memory cell includes a zonal P layer. N.sup.+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N.sup.+ layer and part of the P layer continuous with the N.sup.+ layer, respectively. One side surface of the gate insulating layer is covered with a gate conductor layer continuous with a first plate line, and the other side surface is covered with a gate conductor layer continuous with a second plate line. A gate conductor layer continuous with a word line surrounds the gate insulating layer.

A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.

A semiconductor device and a method for forming the semiconductor device are provided. The method includes the following operations. A semiconductor substrate is provided, the semiconductor substrate includes multiple bit line structures disposed at intervals along a first direction; for each of the multiple bit line structures, surfaces of the bit line structure are filled with a conductive material to form a conductive layer covering the surfaces of the bit line structure. A top surface of the conductive layer is higher than a top surface of the bit line structure; and the conductive layer is etched to form multiple first conductive layers independent of each other and multiple second conductive layers, each of which is located on a respective one of the first conductive layers.

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.

A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.