Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.

A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

The present disclosure relates to the technical field of semiconductor manufacturing, and provides a method of manufacturing a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a substrate; forming a mask layer on the substrate; removing a part of the mask layer on a non-array region; forming a first oxide layer on the non-array region; removing a part of the first oxide layer on a first transistor region, to expose a top surface of the first transistor region; forming an epitaxial layer on the exposed top surface of the first transistor region; removing a part of the first oxide layer on a second transistor region; and forming a second oxide layer on the second transistor region and the epitaxial layer.

The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a shallow trench penetrating through the pad nitride layer and the pad oxide layer and extending into the semiconductor substrate; forming a first liner, a second liner and a third liner over sidewalls and a bottom surface of the semiconductor substrate in the shallow trench; filling a remaining portion of the shallow trench with a trench filling layer over the third liner; and planarizing the second liner, the third liner and the trench filling layer to expose the pad nitride layer. The first liner and the remaining portions of the second liner, the third liner and the trench filling layer collectively form a shallow trench isolation (STI) structure in an array area.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer. The second redistribution structure is disposed over the second integrated circuit structure and the second encapsulation material.

Embodiments of the present disclosure provide a method and a device for determining a fabrication chamber. According to a current radio frequency power time of each of the fabrication chambers corresponding to adjacent process steps and service phases divided based on a service period of the fabrication chambers, a service phase is determined for the current radio frequency power time of each of the fabrication chambers. For target objects processed by the fabrication chambers in the current process step, fabrication chambers for the target objects to enter in a next process step are directly determined according to the service phase of the current radio frequency power time of each of the fabrication chambers.

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.

An indirect heating method using a laser according to an aspect of the present disclosure includes: a first process of adjacently placing a first material structure containing metal and a second material structure containing inorganic material; and a second process of directly heating the first material structure to indirectly heat the second material structure adjacent to the first material structure by radiating a laser to the first material structure.