A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, cell active patterns on the cell region of the substrate, peripheral active patterns on the peripheral region of the substrate, a boundary insulating pattern disposed on the boundary region of the substrate and disposed between the cell active patterns and the peripheral active patterns, and a bumper pattern disposed on the cell region of the substrate and disposed between the boundary insulating pattern and the cell active patterns. A width of the bumper pattern in a first direction parallel to a top surface of the substrate is greater than a width of each of the cell active patterns in the first direction.

A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

A dynamic random access memory includes a substrate, an isolation structure, and a buried word line structure. The isolation structure is located in the substrate and defines multiple active regions. The buried word line structure is located in a word line trench in the substrate, and the word line trench passes through the active regions and the isolation structure. The buried word line structure includes a gate conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The gate conductive layer is located in the word line trench. The first gate dielectric layer is located on a sidewall and a bottom surface of the word line trench. The second gate dielectric layer is located between the first gate dielectric layer and the gate conductive layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductive layer.

Some embodiments include dielectric material having a first region containing HfO and having a second region containing ZrO, where the chemical formulas indicate primary constituents rather than specific stoichiometries. The first region contains substantially no Zr, and the second region contains substantially no Hf. Some embodiments include capacitors having a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material includes one or more first regions and one or more second regions. The first region(s) contain(s) Hf and substantially no Zr. The second region(s) contain(s) Zr and substantially no Hf. Some embodiments include memory arrays.

An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.

A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.