Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.

A semiconductor device includes a substrate including a cell region and a peripheral circuit region; a conductive structure on the cell region and the peripheral circuit region, the conductive structure extending in a first direction parallel to an upper surface of the substrate; a gate structure on the peripheral circuit region, the gate structure spaced apart from the conductive structure in the first direction; a spacer contacting a sidewall of the gate structure; and a first capping pattern contacting a sidewall of an end portion in the first direction of the conductive structure and a sidewall of the spacer, wherein the spacer and the first capping pattern include different insulating materials.

A semiconductor device includes a substrate including a cell area and an interface area surrounding the cell area, the substrate including a device isolation layer defining an active region in the cell area and including an area isolation layer in the interface area, a gate structure extending in the cell area in a first horizontal direction, the gate structure being buried in the substrate and intersecting the active region, a bit line structure intersecting the gate structure and extending in a second horizontal direction intersecting the first horizontal direction, and dummy gate structures extending in the interface area in the first horizontal direction and being spaced apart from one another in the second horizontal direction. The dummy gate structures are buried in the area isolation layer and being spaced apart from the gate structure in the second horizontal direction.

A semiconductor device includes a plurality of pads connected to an external device, a memory cell array in which a plurality of memory cells are disposed, a logic circuit configured to control the memory cell array and including a plurality of input/output circuits connected to the plurality of pads, and at least one inductor circuit connected between at least one of the plurality of pads and at least one of the plurality of input/output circuits. The inductor circuit includes an inductor pattern connected between the at least one of the plurality of pads and the at least one of the plurality of input/output circuits, and a variable pattern disposed between at least portions of the inductor pattern. The variable pattern is separated from the inductor pattern, the at least one of the plurality of pads, and the at least one of the plurality of input/output circuits.

A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

Provided is a semiconductor memory device comprising a device isolation pattern in a substrate and defining first and second active sections spaced apart from each other, wherein a center of the first active section is adjacent to an end of the second active section, a bit line that crosses over the center of the first active section, a bit-line contact between the bit line and the first active section, and a first storage node pad on the end of the second active section. The first storage node pad includes a first pad sidewall and a second pad sidewall. The first pad sidewall is adjacent to the bit-line contact. The second pad sidewall is opposite to the first pad sidewall. When viewed in plan, the second pad sidewall is convex in a direction away from the bit-line contact.

Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.

A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.

Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a substrate, the substrate being provided with a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, and a depth of each of the plurality of first trenches being less than a depth of each of the plurality of second trenches; forming a first isolation structure to cover the substrate and fill the plurality of first trenches and the plurality of second trenches; forming a plurality of third trenches positioned in the substrate at bottoms of the plurality of first trenches and extending along the first direction; forming a second isolation structure to fill the plurality of first trenches and the plurality of third trenches; forming gate structures surrounding the substrate between the plurality of first trenches along the second direction.