A semiconductor memory device includes a substrate, memory layers, a first wiring disposed at a position closer to the substrate than memory layers or a position farther from the substrate than memory layers, a transistor layer disposed between memory layers and the first wiring, and a second wiring connected to the memory layers and the transistor layer. Each of memory layers includes a memory unit, a first semiconductor layer connected between the memory unit and the second wiring, a first electrode opposed to the first semiconductor layer, a third wiring connected to the first electrode, a second semiconductor layer electrically connected to one end portion of the third wiring, and a second electrode opposed to the second semiconductor layer. The transistor layer includes a third semiconductor layer connected between the first wiring and the second wiring, and a third electrode opposed to the third semiconductor layer.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. During a refresh operation, at least one of word lines is selected and a voltage of the channel semiconductor layer of the selected word line is returned to a voltage in a state in which a page is written by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer.

Provided are a thin film structure, a capacitor including the thin film structure, a semiconductor device including the thin film structure, and a method of manufacturing the thin film structure, in which the thin film structure may include: a first electrode thin film disposed on a substrate and including a first perovskite-based oxide; and a protective film disposed on the first electrode thin film and including a second perovskite-based oxide that is oxygen-deficient and includes a doping element. The thin film structure may prevent the deterioration of conductivity and a crystalline structure of a perovskite-based oxide electrode, which is a lower electrode, even in a high-temperature oxidizing atmosphere for subsequent dielectric film deposition.

Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

To provide a semiconductor device with less variations in characteristics. The semiconductor device includes a first circuit region and a second circuit region over a substrate, where the first circuit region includes a plurality of first transistors and a first insulator over the plurality of first transistors; the second circuit region includes a plurality of second transistors and a second insulator over the plurality of second transistors; the second insulator includes an opening portion; the first transistors and the second transistors each include an oxide semiconductor; a third insulator is positioned over and in contact with the first insulator and the second insulator; the first insulator, the second insulator, and the third insulator inhibit oxygen diffusion; and the density of the plurality of first transistors arranged in the first circuit region is higher than the density of the plurality of second transistors arranged in the second circuit region.

Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the present disclosure includes: providing a substrate, the substrate being provided with first trenches arranged in a same direction; forming protective layers on side walls of the first trenches; forming second trenches at bottoms of the first trenches, the second trenches being wider than the first trenches; forming first spacers on side walls of the second trenches to reduce opening sizes of the second trenches; filling the first trenches and the second trenches to form second spacers, and forming voids in the second trenches; forming third trenches in the substrate, the third trenches being perpendicular to the first trenches; and forming bit lines in the third trenches.

Embodiments of the present application provide a method of fabricating a memory, the method comprises: providing a substrate, wherein grooves are disposed in the substrate; forming a gate insulation layer on a surface of each groove; forming a metal layer on the gate insulation layer, the metal layer being at least fully filled in the groove; surface-processing the metal layer, to enhance flatness of a surface of the metal layer; and etching to remove the metal layer by a certain thickness to form a gate electrode whose top is lower than a surface of the substrate. Embodiments of the present application facilitate to solve the problem of unevenness at the top surface of the gate electrode.

The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor base, bit lines and word lines, wherein a plurality of active regions is provided in the semiconductor base; the bit lines are disposed in the semiconductor base, extend in a first direction and are connected to the active regions; and the word lines are disposed on the semiconductor base above the bit lines, extend in a second direction, and intersect with the active regions.

Described herein are three-dimensional transistors with a recessed gate, and IC devices including such three-dimensional transistors with recessed gates. The transistor includes a channel material having a recess. The channel material is formed over a support structure, and source/drain regions are formed in or on the channel material, e.g., one either side of the recess. A gate stack extends through the recess. The distance between the gate stack and the support structure is smaller than the distance between one of the source/drain regions and the support structure. This arrangement increases the channel length relative to prior art transistors, reducing leakage.