Group III oxide semiconducting devices with effective device isolation and edge termination regions.

A method of making a semiconductor device is provided. A monolithic die having at least two semiconductor dies is provided. Each of the at least two semiconductor dies includes a substrate and an epitaxial layer formed on the substrate. An isolation structure is formed electrically isolating two semiconductor dies of the at least two semiconductor dies. The isolation structure traverses the thickness of the substrate and the epitaxial layer and includes a first isolation trench.

A semiconductor structure includes a Schottky diode structure, which includes: a first trench extending through a first N-type semiconductor layer and being disposed in the first N-type semiconductor layer; a first insulating layer disposed in the first trench; two polysilicon layers or metal silicide layers disposed in the first trench, wherein an upper one and a lower one of the polysilicon layers or metal silicide layers are disposed in parallel; a first P-type protective layer, which is grounded and disposed on a bottom of the first trench, and contacts the first insulating layer and a bottom surface of the lower one of the polysilicon layers or metal silicide layers; a metal layer respectively disposed as a top surface and a lower bottom surface of the semiconductor structure to form a source and a drain as electrodes for the semiconductor structure to be connected to an external device.

A method of fabricating a semiconductor device includes forming an epitaxial layer on a substrate, forming first and second doped regions in the epitaxial layer, forming a trench to expose the first and second doped regions, conformally forming a first dielectric layer in the trench, and forming first and second spacers on opposite sidewalls of the trench. The first dielectric layer is etched by using the first and second spacers as a mask to form an opening, thereby exposing portions of the epitaxial layer and the first and second doped regions. A lower conductive portion is formed in the trench and the opening to contact the portion of the epitaxial layer. A dielectric isolation portion and an upper conductive portion are formed in the trench. The upper and lower conductive portions are separated by the dielectric isolation portion.

There is provided a diode including an anode electrode provided on a side of a front surface of a semiconductor substrate, an interlayer dielectric film disposed between the semiconductor substrate and the anode electrode, a first anode region of a first conductivity type provided on the front surface of the semiconductor substrate, a second anode region of a second conductivity type, which is different from the first conductivity type, provided on the front surface of the semiconductor substrate, a first contact hole provided in the interlayer dielectric film, causing the anode electrode to be in Schottky contact with the first anode region, and a second contact hole provided in the interlayer dielectric film and different from the first contact hole, causing the anode electrode to be in ohmic contact with the second anode region.

A Schottky diode includes a drift layer of a first conductivity type, a trench in the drift layer, first implanted regions having a second conductivity type in sidewalls of the trench, a second implanted region having the second conductivity type in a bottom of the trench, and a metal in the trench. The first implanted regions have a first doping concentration and the second implanted region has a second doping concentration, wherein the first doping concentration is different than the second doping concentration.

A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.

A semiconductor chip has a first semiconductor layer, a second semiconductor layer formed on an upper surface of the first semiconductor layer, and a semiconductor region formed in the second semiconductor layer. A trench is formed in the semiconductor region. An insulating film is formed on each of an upper surface of the second semiconductor layer and an inner surface of the trench. A polysilicon film is formed on the insulating film so as to embed an inside of the trench. A front surface electrode made of metal is formed on the polysilicon electrode, and a back surface electrode made of metal is formed on a lower surface of the first semiconductor layer. An impurity concentration of the second semiconductor layer located between the semiconductor region and the first semiconductor layer is lower than an impurity concentration of each of the first semiconductor layer and the semiconductor region.

A semiconductor device includes an epitaxial layer disposed on a substrate. The substrate includes a first region and a second region, where the first region is a drain region and the second region is a cathode. A first trench, a second trench and a third trench are disposed in the epitaxial layer. A gate includes a planar conductive portion on the epitaxial layer and a first trench conductive portion in the first trench. A source region is disposed in the epitaxial layer and on sides of the first trench. An anode is disposed on the epitaxial layer and between the second and third trenches. A first heavily doped region is disposed in the epitaxial layer and directly below the anode, and includes a first portion abutting the second trench and a second portion abutting the third trench.

The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. A structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures.