Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. One or more heavily doped regions of the second conductivity type are formed through portions of the first buffer layer from the second buffer layer and into corresponding portions of the substrate. This abstract is provided with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. The p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode. Breakdown of a portion of a gate insulating film immediately below the center of the gate pad electrode and breakdown of the semiconductor device are thus prevented

A semiconductor device includes a semiconductor chip formed with an SiC-IGBT including an SiC semiconductor layer, a first conductive-type collector region formed such that the collector region is exposed on a second surface of the SiC semiconductor layer, a second conductive-type base region formed such that the base region contacts the collector region, a first conductive-type channel region formed such that the channel region contacts the base region, a second conductive-type emitter region formed such that the emitter region contacts the channel region to define a portion of a first surface of the SiC semiconductor layer, a collector electrode connected to the collector region, and an emitter electrode connected to the emitter region. A MOSFET of the device is connected in parallel to the SiC-IGBT, and includes a second conductive-type source region electrically connected to the emitter electrode and a second conductive-type drain region electrically connected to the collector electrode.

This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*N.sub.D*W.sub.N=q*N.sub.A*W.sub.P and a punch through condition of W.sub.P<2*W.sub.D*[N.sub.D/(N.sub.A+N.sub.D)] where N.sub.D and W.sub.N represent the doping concentration and the thickness of the N type layers 160, while N.sub.A and W.sub.P represent the doping concentration and thickness of the P type layers; W.sub.D represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.

The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is generally expressed with C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2) . There are provided a high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, a manufacturing apparatus of such an SiC epitaxial wafer, a fabrication method of such an SiC epitaxial wafer, and a semiconductor device.

A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.

A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2.sup.nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.

A power semiconductor device includes a power transistor including a plurality of transistor cells on a semiconductor die. At least some of the transistor cells are inhomogeneous by design so that the number of current filaments in the transistor cells with reduced local current density increases and fewer transient avalanche oscillations occur in the power transistor during operation.