An insulated gate bipolar transistor includes a semiconductor substrate, and the semiconductor substrate includes: a collector region doped in a first type, wherein the collector region includes a bump region; a first drift region doped in a second type and a second drift region doped in the second type; wherein the first drift region and the second drift region locate on a side of the collector region having the bump region, a profile contour of the first drift region matches a profile contour of the bump region, such that the second drift region does not contact the bump region, and a doping concentration of the first drift region is greater than a doping concentration of the second drift region; and a first active region and a second active region, formed at two opposite ends of the second drift region.

Provided is a semiconductor device, including: a trench portion which is provided in an upper surface side of a semiconductor substrate, a cathode region of a first conductivity type or a collect region of a second conductivity type which is provided in a lower surface side of the semiconductor substrate, a buffer region of the first conductivity type which is provided between a lower end of the trench portion and the cathode region or the collect region, and has a first peak, a second peak, a third peak and a fourth peak higher than a bulk donor concentration of the semiconductor substrate in a doping concentration distribution in a depth direction.

Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650 C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 110.sup.16 cm.sup.3 to about 510.sup.18 cm.sup.3. The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm.sup.2/V-s at a gate voltage of 25V.

A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical conductance; forming grooves at intervals on the first surface of the substrate; filling a semiconductor material of the second or first type of electrical conductance into the grooves to form channels, where the type of electrical conductance of the channels is different from the type of electrical conductance of the substrate; bonding on the first surface of the substrate to form a drift region of the second type of electrical conductance; forming a front-side structure of the IGBT on the basis of the drift region; thinning the substrate starting from the second surface of the substrate until the channels are exposed; and forming a rear-side metal electrode on the channels and the thinned substrate. The method has no specific requirement with respect to sheet flow capacity, nor requires a double-sided exposure machine apparatus, is compatible with a conventional process, and has a simple process and high efficiency.

A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad. Thus, measurement of the gate resistance value and selection from gate resistances of the switching element can be performed after the completion of the gate-resistor-incorporating-type switching element.

Semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a Schottky junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the pn junction diode is greater than 100 V and a breakdown voltage of the Schottky junction diode is greater than 10 V.

An embodiment of a method of manufacturing a semiconductor device includes forming an oxygen diffusion barrier on a first surface of a Czochralski or magnetic Czochralski silicon substrate. A silicon layer is formed on the oxygen diffusion barrier. P-doped and n-doped semiconductor device regions are formed in the silicon layer. The method also includes forming first and second load terminal contacts.

We disclose herein a method of manufacturing a silicon carbide (SiC) based insulated gate bipolar transistor (IGBT), the IGBT comprising: a monocrystalline silicon substrate; a collector region of a first conductivity type disposed over the silicon substrate, wherein the collector region comprises a material comprising 3-step cubic silicon carbide (3C-SiC); a semiconductor drift region of a second conductivity type, opposite the first conductivity type, disposed on the collector region; a body region of the first conductivity type located within the semiconductor drift region; an emitter region of the second conductivity type located within the body region; a gate region placed above and in contact to the emitter region. The method comprising: providing the silicon substrate having a principal surface, wherein the silicon substrate is of the second conductivity type; doping the principal surface of the silicon substrate using an aluminium ion implant; and driving the aluminium ion implant into the silicon substrate to a predetermined depth under a predetermined temperature so that a heavily doped silicon region of the first conductivity type is formed near the principal surface within the silicon substrate.

A method of forming a transistor device include forming a drift layer of a first conductivity type, forming a well of a second conductivity type in the drift layer, forming a JFET region with first conductivity type dopant ions in the drift layer, forming a channel adjustment layer of the first conductivity type on the JFET region and the well, implanting first conductivity type dopant ions to form an emitter region of the first conductivity type extending through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the JFET region by the well, implanting second conductivity type dopant ions to form a connector region of the second conductivity type adjacent the emitter region, forming a gate oxide layer on the channel region, and forming a gate on the gate oxide layer.