Reverse-conducting semiconductor device

Abstract

A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

Claims

1. A Reverse-conducting semiconductor device, which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness, wherein the insulated gate bipolar transistor comprises a collector side and an emitter side opposite to the collector side of the wafer, wherein the base layer thickness is the maximum vertical distance between the collector and emitter side of that part of the wafer with the first doping concentration, a cathode layer of the first conductivity type and higher doping concentration than the first doping concentration, and an anode layer of a second conductivity type, which is different from the first conductivity type, are alternately arranged on the collector side, wherein a plurality of source regions of the first conductivity type, a well layer of the second conductivity type and a gate electrode having an electrically conductive gate layer, which is insulated from any layer of the first or second conductivity type by a first insulating layer, are arranged on the emitter side, wherein the cathode layer comprises at least one first region, wherein each first region has a first region width, wherein the anode layer comprises at least one second region, wherein each second region has a second region width, and at least one pilot region, wherein each pilot region has a pilot region width, wherein any region has a region width and a region area, which is surrounded by a region border, wherein a shortest distance is the minimum length between a point within said region area and a point on said region border, each region width is defined as two times the maximum value of all shortest distances within said region, the reverse-conducting semiconductor device comprises an active region in a central part of the device, which active region is an area within the wafer, which includes and is arranged in projection of the source region, well layer and gate layer, wherein each pilot region area is an area having a width of at least two times the base layer thickness, wherein the pilot region is laterally surrounded on the pilot region border by first regions, which have a distance from each other of less than two times the base layer thickness, wherein the at least one second region is that part of the anode layer, which is not the at least one pilot region, wherein a mixed region comprises the at least one first and second regions, wherein the at least one pilot region is arranged in the central part of the device such that the mixed region laterally surrounds the at least one pilot region, wherein the mixed region has a width of at least once the base layer thickness, wherein the total area of the at least one pilot region is between 10% and 45% of the area of the mixed region, wherein each first region width is smaller than the base layer thickness, in each area on the emitter side, which lies in projection to one of the at least one pilot region, the plurality of source regions have a first area density, wherein in each area on the emitter side, which lies in projection to the mixed region, the plurality of source regions have a second area density, wherein the first area density is lower than the second area density.

2. The Reverse-conducting semiconductor device according to claim 1, wherein the first area density is at most 50% of the second area density.

3. The Reverse-conducting semiconductor device according to claim 2, wherein the total area of the first region to the area of the second region plus pilot region is between 10% and 45%.

4. The Reverse-conducting semiconductor device according to claim 1, wherein the first area density is zero.

5. The Reverse-conducting semiconductor device according to claim 1, wherein a gate pad for an external contact of the gate electrode is arranged on the emitter side overlapping a projection to one of the at least one pilot region.

6. The Reverse-conducting semiconductor device according to claim 1, wherein at least one or each second region width is larger than the base layer thickness.

7. The Reverse-conducting semiconductor device according to claim 1, wherein each pilot region area has a width of at least 2.5 times the base layer thickness.

8. The Reverse-conducting semiconductor device according to claim 1, wherein the pilot region has a square, rectangular, circular, star, diamond or hexagon shape.

9. The Reverse-conducting semiconductor device according to claim 8, wherein the pilot region has one of a star shape with three protrusions forming a tri-star, four protrusions forming a cross or five or more protrusions.

10. The Reverse-conducting semiconductor device according to claim 1, wherein the at least one pilot region is connected to at least one or each second region.

11. The Reverse-conducting semiconductor device according to claim 10, wherein the at least one pilot region is one of a single pilot region or at least two pilot regions interconnected to each other via second regions and wherein the single pilot region or the at least two pilot regions are connected to second regions, which extend to the border of the active region.

12. The Reverse-conducting semiconductor device according to claim 1, wherein the total area of the first regions to the area of the second region plus pilot region is between 10% and 45%.

13. The Reverse-conducting semiconductor device according to claim 1, wherein the total area of the at least one pilot region is between 18% and 33% of the mixed region.

14. The Reverse-conducting semiconductor device according to claim 1, wherein the at least one pilot region consists of one of a single region or the at least one pilot region comprises a plurality of regions which are separated from each other by at most twice the base layer thickness.

15. The Reverse-conducting semiconductor device according to claim 14, wherein the at least one pilot region comprises a plurality of regions which are separated from each other by at most once the base layer thickness.

16. The Reverse-conducting semiconductor device according to claim 1 wherein the mixed region has a width of at least twice the base layer thickness.

17. The Reverse-conducting semiconductor device according to claim 1, wherein the gate electrode is formed as one of a trench gate electrode or a planar gate electrode.

18. The Reverse-conducting semiconductor device according to claim 1, wherein each pilot region area has a width of between 3 and 4 times the base layer thickness.

19. The Reverse-conducting semiconductor device according to claim 1, wherein the first area density is at most 10% of the second area density.

20. The Reverse-conducting semiconductor device according to 1, wherein the total area of the at least one pilot region is between 22 and 28% of the mixed region.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The subject matter of the invention will be explained in more detail in the following text with reference to the attached drawings, in which:

(2) FIG. 1 shows a cross sectional view on a prior art reverse-conducting IGBT;

(3) FIG. 2 shows a plan view of the structures of first and second regions of a reverse-conducting IGBT according to the invention;

(4) FIG. 3 shows a plan view of the structures of first and second regions of another reverse-conducting IGBT according to the invention;

(5) FIGS. 4 and 5 shows plan views of the structures of cathode layer with first regions and anode layer with second and pilot regions and a gate pad of other reverse-conducting IGBTs according to the invention;

(6) FIGS. 6-8 shows plan views of the structures of cathode layers with first regions and anode layer with second and pilot regions of other reverse-conducting IGBTs according to the invention;

(7) FIG. 9 shows the layers on the emitter side of another inventive reverse-conducting IGBT with trench gate electrodes;

(8) FIG. 10 shows the layers on the emitter side of another inventive reverse-conducting IGBT with an enhancement layer;

(9) FIGS. 11-16 show plan views of the structures of cathode layers with first regions and anode layer with second and pilot regions of other reverse-conducting IGBT according to the invention; and

(10) FIGS. 17-19 show plan views of the structures of cathode layers with first regions and anode layers with second and pilot regions of other reverse-conducting IGBT according to the invention;

(11) FIGS. 20-21 show carrier plasma (hole density) concentration in the prior art devices in a plane located 5 m from the emitter during IGBT mode turn-off; and

(12) FIG. 22 shows an example of a BIGT turn-off waveform showing the onset of dynamic avalanche; and

(13) FIG. 23 shows a cross sectional view on of a reverse-conducting IGBT according to the invention.

(14) The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.

MODES FOR CARRYING OUT THE INVENTION

(15) In FIG. 1 a first embodiment of an inventive reverse-conducting semiconductor device 200, also named reverse-conducting insulated gate bipolar transistor (RC-IGBT) is shown. The RC-IGBT 200 comprises an n type base layer 101 with a first main side, which forms the emitter side 104 of the integrated IGBT, and a second main side opposite the first main side, which forms the collector side 103 of the integrated IGBT. The base layer 101 is that part of an (n) doped wafer 100, which has a first low doping concentration, typically the un-amended doping in the finalized reverse-conducting insulated gate bipolar transistor. Alternatively, the device could also be manufactured starting from a p doped wafer, on which the base layer 101 is created, e.g. by epitaxial growing. In an exemplary embodiment, the base layer thickness 102 is the maximum vertical distance between the collector and emitter sides 103 and 104 of that part of the wafer with the first doping concentration (i.e. of the base layer 101). In an exemplary embodiment, the base layer thickness is at least 100 m (for a device of about 1200 V), at least 300 m (for a device of about 2500 V) and at least 500 um (for a device of about 4500 V).

(16) A p type well layer 4 is arranged on the emitter side 104. At least one n type source region 3 is also arranged on the emitter side 104 and it is surrounded by the well layer 4. The at least one source region 3 has a higher doping than the base layer 101. An electrically insulating layer 6 is arranged on the emitter side 104 on top of the base layer 101, the well and source region 4, 3. It at least partially covers the at least one source region 3, the well layer 4 and the base layer 101. An electrically conductive gate layer 5 is arranged on the emitter side 104 electrically insulated from the at least one well layer 4, the source region 3 and the base layer 101 by an insulating layer 6. Exemplarily, the gate layer 5 is completely covered by the insulating layer 6.

(17) Typically the insulating layer 6 comprises a first electrically insulating layer 61, preferably made of a silicon dioxide, and a second electrically insulating layer 62, preferably also made of a silicon dioxide, preferably of the same material as the first electrically insulating layer 61. The second electrically insulating layer 62 covers the first electrically insulating layer 61. For an RC-IGBT 200 with a gate layer 5 formed as a planar gate electrode 5 as shown is FIG. 1 the first electrically insulating layer 61 is arranged on top of the emitter side 104. In between the first and second electrically insulating layers 61, 62, which form the insulating layer 6, the gate layer 5, is embedded, typically it is completely embedded. Thus, the gate layer 5 is separated from the base layer 101, the source region 3 and the well layer 4 by the first electrically insulated layer 61. The gate layer 5 is typically made of a heavily doped polysilicon or a metal like aluminum. The planar gate electrode 5 comprises the gate layer 5 and the insulating layer 6.

(18) The at least one source region 3, the gate layer 5 and the insulating layer 6 are formed in such a way that an opening is created above the well layer 4. The opening is surrounded by the at least one source region 3, the gate layer 5 and the insulating layer 6.

(19) An emitter electrode 8 is arranged on the emitter side 104 within the opening so that it is in direct electrical contact to the well layer 4 and the source region 3. This emitter electrode 8 typically also covers the insulating layer 6, but is separated and thus electrically insulated from the gate layer 5 by the second electrically insulating layer 62.

(20) An n type cathode layer 1 and a p type anode layer 2 are arranged on the collector side 103 and the cathode layer 1 has a higher doping concentration than the first doping concentration of the base layer 101. The cathode and anode layers 1, 2 can be arranged in the same plane or, alternatively, they can also be arranged in different planes, whereas the planes from the cathode and anode layer 1, 2 are spaced from each other, preferably at least by the thickness of that layer, which is arranged farer away from the collector side 103. Devices with such cathode and anode layers 1, 2 being arranged in different planes and their manufacturing methods are known from the European patent applications with filing numbers EP 07150162 and EP 07150165.

(21) The semiconductor device comprises an active region 110 (central region) in a central part of the device 200 and a termination region 111, which surrounds the active region 110 up to the edge of the substrate or chip. The active region 110 is the area in which the device conducts current during on-state, in the case of an IGBT this is the MOS cell. The active region is that area within the wafer 100, which includes the source region 3 and well layer 4 and is arranged below the source region 3, well layer 4 and gate layer 5. With below the area is meant which is arranged in the wafer 100 between the emitter side 104 and the collector side 103, in which area any of the source region 3, well layer 4 or gate layer 5 are arranged.

(22) In the termination area 111, typically first and second regions 10, 20 are arranged on the collector side 103, but alternatively this region may also consist of a single n doped region or of a single p doped region. Within the termination area, where first and second regions 10, 20, or only the single n or p region on the collector side 103 are arranged, neither a source region 3, a well layer 4 nor a gate electrode is arranged on the emitter side 104.

(23) A collector electrode 9 is arranged on the collector side 103 and it is in direct electrical contact to the at least one cathode and anode layers 1, 2. Typically, Ti, Ni, Au or Al are chosen as a material for the collector electrode 9.

(24) In the inventive RC-IGBT 200 a diode is formed between the emitter electrode 8, which forms an anode electrode in the diode, the well layer 4, part of which forms an anode layer of the diode, the base layer 101, part of which forms a base layer for the diode, the n type cathode layer 1 and which layer forms a cathode layer, and the collector electrode 9, which forms a cathode electrode.

(25) In the inventive RC-IGBT 200 an insulated gate bipolar transistor (IGBT) is formed between the emitter electrode 8, which forms an emitter electrode in the IGBT, the source region 3, which forms a source region, the well layer 4, part of which forms a channel region, the base layer 101, part of which forms a base region for the IGBT, the p type anode layer 2, and the collector electrode 9, which forms a collector electrode.

(26) Alternatively to the inventive RC-IGBT with a planar gate electrode 5, the inventive RC-IGBT may comprise a gate layer 5, formed as trench gate electrode 5 as shown in FIG. 9. The trench gate electrode 5 is arranged in the same plane as the well layer 4 and adjacent to the source region 3, separated from each other by a first insulating layer 61, which also separates the gate layer 5 from the base layer 101. A second insulating layer 62 is arranged on top of the gate layer 5 formed as a trench gate electrode 5, thus insulating the gate layer 5 from the emitter electrode 8.

(27) Any of the first, second and pilot regions has a region width and a region area, which is surrounded by a region border.

(28) In an exemplary embodiment, a shortest distance is the minimum length between a point within said region area and a point on the region border. The region width is measured in a plane parallel to the collector side 103. Each region width in this exemplary embodiment is defined as two times the maximum value of all shortest distances within said region.

(29) The n type cathode layer 1 comprises at least one or a plurality of first regions 10, wherein each first region 10 has a first region width 11. Typically the cathode layer 1 comprises a plurality of first regions 10.

(30) The p type anode layer 2 comprises at least one or a plurality of second regions 20 and at least one or a plurality of pilot regions 22, wherein each second region 20 has a second region width 21 and the pilot region 22 has a pilot region width 23.

(31) FIG. 2 shows a cut through the cathode and anode layer 1, 2 along the line B-B from FIG. 1. This line is also indicated in FIG. 2 in order to show that the RC-IGBT does not have the same structure for the cathode and anode layer 1, 2 over the whole plane of the wafer 100. There are parts in which the cathode and anode layer 1, 2 only comprises first and second regions 10, 20 as shown in FIGS. 2 and 3 and which are also present in the FIGS. 6, 7 and 8 e.g. along the line B-B. In other parts of the RC-IGBT 200, the on the collector side 103, only a pilot region 22 is arranged, which contacts the collector electrode 9.

(32) Each pilot region area is an area, in which any two first regions 10, which are arranged on the border of the pilot region 22, have a distance between two neighboured first regions 10 on the pilot region border smaller than two times the base layer thickness 102. That means that the at least one first region 10 surrounds the at least one pilot region 22 in a plane parallel to the emitter side 104 such that an n doped area (i.e. first region(s)), which has at least one opening (i.e. in which p doped second regions 20 are arranged) of less than two times the base layer thickness 102 or which has no such openings, surrounds the at least one pilot region 22. This shall include the option that the first region 10 is a continuous region surrounding the pilot region 22 in a plane parallel to the emitter side 104 or by having a first region formed as an open ring having an opening smaller than two times the base layer thickness 102. By having an n doped area around the pilot region 22, p doped areas have a width of less than two times the base layer thickness 201 (and thus form second regions 20) are arranged.

(33) In the pilot region 22, no first region is arranged or enclosed. Across the pilot region 22, the first regions 10 have a distance of more than two times the base layer thickness 102. That means that the pilot region 22 may be enclosed by first regions 10 which have a smaller distance to each other, but across the pilot region area, the distance between any two first regions 10 may be larger than two times the base layer thickness 102. In other exemplary embodiments, each pilot region area has a width larger than 2.5, in particular 3 times or 4 times the base layer thickness 102. The at least one second region is that part of the anode layer 2, which is not the at least one pilot region 22.

(34) The pilot region 22, i.e. the p doped area, in which the width is bigger than two times the base layer thickness 102, is arranged in the central part of the device in such a way that there is a minimum distance between the pilot region border to the interface between the active region and the termination region of at least once the base layer thickness 102, in particular twice the base layer thickness 102. The sum of the areas (total area) of the at least one pilot region 22 is between 10% and 45% of the area of the mixed region 10, 20, exemplarily between 11 and 43%. Furthermore, each first region width 11 is smaller than the base layer thickness 102.

(35) For a device, in which in projection to the pilot region 22 source regions 3 are arranged, the pilot region 22 becomes part of the active region 110 and the pilot region area may be between 10 to 30% of the active region area.

(36) The pilot region has a pilot region area such that a circle (p doped area) having a diameter of at least two times the base layer thickness 102 can be laid into the pilot region over the whole region area in a plane parallel to the emitter side 104. No n doped region 10 is enclosed in this p doped pilot region 22. The first regions 10 are arranged on the pilot region border in a distance from each other smaller than twice the base layer thickness 102, exemplarily once the base layer thickness 102.

(37) In an exemplary embodiment, the width of the pilot region may be at least 200 m, at least 500 m or at least 1000 m. In another exemplary embodiment, the pilot region width may be at least 2, 2.5, 3 or 4 times the base layer thickness 102.

(38) The second regions 20 and the first regions 10 form shorted regions. The second regions 20 are p doped regions, which are not a pilot region 22. In another exemplary embodiment, at least one second region width 21 is equal to or larger than one time the base layer thickness 102 (but smaller than two time the base layer thickness 102), in particular each second region width 21 is equal to or larger than the base layer thickness 102, and each first region width 11 is smaller than the base layer thickness 102.

(39) In another exemplary embodiment the total area of the second and pilot regions 20, 22 to total area of the wafer 100 in the central region (i.e. pilot region area plus first and second region area, which is part of active region 110) is between 70% up to 90%. In such a device the total area of the first regions 10 to the area of the second region 20 plus pilot region 22 is between 10% to 45% (which corresponds to 10 to 30% of the central area).

(40) In a further preferred embodiment the total area of the at least one pilot region 22 is between 18 to 33% and exemplarily between 22 to 28% % of the mixed region (i.e. 15 to 25 or 18 to 22, around 20% of the central area).

(41) Typical designs for the first and second regions 10, 20 are a stripe design (as shown in FIGS. 2, 17 and 22, 23) However, any appropriate design may be used for the first and second regions.

(42) The widths 11, 21 of the shorted first and/or second regions 10, 20 can be constant over the whole wafer area so that the first and pilot regions 10, 20 are arranged in a regular geometrical manner over the wafer 100 as e.g. shown in the FIGS. 2 and 3, but their widths may also vary over the wafer 100. In case of the second regions 20 being formed as stripes, the stripes can be surrounded be first regions as shown in FIG. 3.

(43) In the FIGS. 17 to 19 only the active region 110 of the device is shown. The termination region 111, in which typically first and second regions 10, 20 are arranged, but alternatively this region may also consist of an n doped region or of a p doped region, surrounds the active region 110.

(44) By the presence of a large pilot region 22 in the device the initial snap-back is removed. As the remaining second regions 20 have smaller dimensions, a secondary snap-back may be present when these p doped regions are turned on one after the other and cause negative resistance jumps in the on-state characteristics. By having a second region 20 with a greater width close to the pilot region and by decreasing the widths of the subsequent second regions, a smooth transition is achieved, by which the snap-back effect is further lowered or even avoided.

(45) In each area on the emitter side 104, which lies in projection (directly opposite) to a pilot region 22, the plurality of source regions 3 have a first area density 31. In each area on the emitter side 104, which lies in projection to the mixed region (first and second regions 10, 20), the plurality of source regions 3 have a second area density 31. The first area density 31 is lower than the second area density 32. That means that in the projection of the pilot region 22 on the emitter side 104, either no source region is arranged or at least the area density of the source regions is much smaller than in a projection of the mixed region. In projection shall mean that an area or layer is arranged parallel to another layer/area and to the collector side 103. The layers/areas lie directly opposite to each other without a lateral shift.

(46) In other exemplary embodiments, the first area density 31 is lower than 50% or lower than 10% or lower than 5% of the second area density 32. In another exemplary embodiment, there is no source region 3 arranged in projection to the pilot region 22. In this case, the region in projection to the pilot region 22 does not contribute to the active region 110 of the device, but the pilot region 22 is enclosed by the mixed region 10, 20, which is part of the active region 110.

(47) FIG. 23 shows a cross sectional view on an inventive RC-IGBT. In the middle part of the figure, a pilot region 22 is arranged, above which (i.e. in projection to which) the source regions 3 have a reduced first area density 31 compared to second area density 32 in the area, in which mixed first and second regions 10, 20 are arranged on the collector side 103. For clarity reasons, in the figures on the emitter side 104 MOS cells 250 are shown substitutionally for the source regions 3 and thus, for the density of the source regions 31, 32. Each MOS cell 250 comprises a gate electrode 5, source region 3 and well layer 4 as well as a contact of the source region 3 and well layer 4 to the emitter electrode 8 so that a channel is formable from the emitter electrode 8 to the base layer 101. The figure shows a reduced first are density 31, but above the pilot region 22 also no source regions at all may be arranged.

(48) In this area opposite to a pilot region 22, i.e. in projection to the pilot region 22, a gate pad 55 for an external contact of the gate electrode 5 may be arranged on the emitter side 104 (FIG. 4). A gate pad 55 is used for electrically connecting the gate electrode 5 to an external contact. Such a gate pad 55 is exemplarily arranged in the active region 110 of the device. As in this region no or at least a reduced area is used for the source regions, space is available for such a gate pad 55, freeing active area where it is needed. Alternatively, such a gate pad 55 may be arranged independently at any other place within the active region 110, e.g. in a corner of the active region 110 (FIG. 5).

(49) In an exemplary embodiment, the pilot region 22 consists of a single region (as shown in the FIGS. 6, 7, 8, 11, 12 and 13). The pilot region may alternatively also comprise a plurality of regions, which are separated from each other by at most twice the base layer thickness 102, in particular by at most one time the base layer thickness 102 (FIGS. 14, 15, 16). In case of the pilot region 22 comprising a plurality of regions, typically first regions 10 are arranged between two regions belonging to the pilot region 22 or at least the intermediate space comprises first regions 10, i.e. the intermediated space comprises first and second regions 10, 20.

(50) In another exemplarily embodiment the first regions 10 are arranged as stripes over the wafer 100. A plurality of stripes is arranged in a row and a plurality of such rows are arranged in columns within the active region 110 (FIG. 2).

(51) In another exemplary embodiment the pilot region 22 is connected to each second region 20 within the active region 110 (FIG. 17).

(52) The pilot region or regions 22 has in another preferred embodiment a square, rectangular, circular, star, diamond, tri-star or polygonal shape like a hexagon or another polyangular design.

(53) FIG. 6 shows such a pilot region 22 with a square shape, whereas FIG. 7 shows a pilot region 22 with a circular shape. In the FIGS. 6 to 8, the first and second regions 10, 20 are only indicated by hatching of the area designated with 10, 20 for clarity reasons, but the hatched area is meant to be an area of alternating first and second regions 10, 20 as e.g. shown in FIGS. 2 and 3.

(54) A shortest distance is the minimum length between a point within said region area and a point on said region border. The maximum value of all possible shortest distances (i.e. any possible distance) within said region is for a square design (FIG. 6) the distance between the central point of the square to the middle point of any of the border lines. This is the longest distance to equalize charge during switching of the device. The region width is defined as two times this maximum value, i.e. the width is the length of the edge of the square.

(55) For a circular shape of the pilot region 22 as shown in FIG. 7 the pilot region width 23 corresponds to the diameter of the pilot region (again the maximum value is measured from the central point of the circle to any point on the border of the circular pilot region.

(56) By the pilot region 22 having a star shape with elongated fingers (protrusions) as for example with the cross shape the heat distribution can be improved, because the heat produced in this IGBT area without the necessity of increasing the size of the pilot region 22. Star shape shall mean any central area of a region, which is surrounded by protrusions (fingers) with at least three such protrusions. A cross as shown in FIG. 8 is formed by four such protrusions. Of course, also another number of fingers than four can be used in a star design as three fingers in a triangle (three armed star or tri-star shape) or five or more fingers in the star design.

(57) In an exemplary embodiment, fingers shall be understood as areas, in which the width is smaller than the length of that area. Such fingers can be formed as a cross (FIG. 8), but of course also another number of fingers than 4 can be used as three fingers in a triangle or 5 or more fingers in a star design.

(58) FIG. 8 show the second pilot region 22 in form of a cross. For explaining what the maximum value (pilot region width 23) of the shortest distance is for this case, the cross is hypothetically divided into four outer rectangles and a central rectangle. The maximum value of any shortest distance between a point within the cross region to the border of the cross region exists from the middle point of the central rectangle of the cross to one of the four points, on which two adjacent outer rectangles adjoin. The pilot region width 23, which is two times this maximum value, is shown as a dashed line. The maximum value is the longest way an electron or hole has to flow in order to charge or discharge the region if the device is switched between on/off or vice versa.

(59) FIG. 18 shows another exemplary embodiment of the inventive device, in which the pilot region 22 in square design is connected to second regions 20, which extend to the border of the active region 110. In case of the device comprising a plurality of pilot regions 22, these regions 22 are interconnected to one another by second regions 20. In another exemplary embodiment, the second regions 20, which expand to the border of the active region 110, are arranged radial between the at least pilot region and the border of the active region. By radial it is meant that the second regions are arranged star like around the pilot region 22 such that the second regions are short connections to the border of the active region. FIG. 19 shows the pilot region in a cross design and FIG. 17 in a stripe design. In these figures, only a part of the second regions radiate from the pilot region border to the active region border and thus form shortest connections. E.g. in the corners of a square, rectangle or a star, the second regions extend such that the distance between the first regions does not get to large (i.e. the geometrical rules for first region distances are fulfilled).

(60) By the presence of a large pilot region as a pilot region in the device with a width of at least two times the base layer thickness the initial snap-back is removed. Due to the smaller size of the second regions a secondary snap-back may be present when these p doped regions are turned on one after the other and cause negative resistance jumps in the on-state characteristics, if the second regions are disconnected from the pilot region. By having the pilot region connected to second regions, and by radial extending the second regions between the pilot region to the interface between the active region and the termination region, the snap-back effect is further lowered or even avoided.

(61) As also shown in FIG. 1, in another embodiment the RC-IGBT 10 may further comprise an n type buffer layer 7, which is arranged between the base layer 101 and the cathode and anode layer 1, 2 respectively, and which buffer layer 7 has a higher doping concentration than the base layer 101.

(62) The buffer layer 7 has preferably a maximum doping concentration of at most 1*10.sup.16 cm.sup.3.

(63) In another preferred embodiment shown in FIG. 10, an n doped enhancement layer 41 is arranged between the well layer 4 and the base layer 101 for having lower on-state losses. The enhancement layer 41 separates the well layer 4 from the base layer 101 and it has higher doping concentration than the base layer 101. The enhancement layer 41 can be present in planar gate designs as well as in trench gate designs.

(64) In another embodiment, the conductivity types of the layers are switched, i.e. all layers of the first conductivity type are p type (e.g. the base layer 101) and all layers of the second conductivity type are n type (e.g. the well layer 4).

(65) The inventive reverse-conducting semiconductor device 200 can for example be used in a converter.

REFERENCE LIST

(66) 1 cathode layer

(67) 10 first region

(68) 11 width of first region

(69) 2 anode layer

(70) 20 second region

(71) 21 width of second region

(72) 22 pilot region

(73) 23 width of pilot region

(74) 3 source region

(75) 31 First area density

(76) 32 Second area density

(77) 4 well layer

(78) 41 enhancement layer

(79) 5, 5 gate layer

(80) 55 gate pad

(81) 6 insulating layer

(82) 61 first electrically insulating layer

(83) 62 second electrically insulating layer

(84) 7 buffer layer

(85) 8 emitter electrode

(86) 9 collector electrode

(87) 100 wafer

(88) 101 base layer

(89) 102 base layer thickness

(90) 103 collector side

(91) 104 emitter side

(92) 110 Active region

(93) 111 termination area

(94) 112 Distance between pilot region border to active region border

(95) 200 RC-IGBT

(96) 250 MOS cell