According to one embodiment, a semiconductor device includes first to third electrodes, a first wiring member, a semiconductor member, and an insulating member. The first wiring member includes a first extending portion. A part of the third electrode is between the first electrode and the first extending portion. An other part of the third electrode is between the first and second electrodes. The semiconductor member is provided between the first and second electrodes and between the first electrode and the first extending portion. The semiconductor member includes first to sixth semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is located between the first electrode and the third electrode. The insulating member includes the first insulating region. The first insulating region is provided between the third electrode and the semiconductor member.

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), whereinthe semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and comprises a well region (22) located next to the first region (21), the first region (21) is of a first conductivity type and the well region (22) is of a second conductivity type, the well region (22) is separated from the gate electrode (33) by a gate insulator layer (4), the first region (21) is electrically contacted by means of the first electrode (31), in the first region (21) there is at least one current limiting region (5), andthe at least one current limiting region (5) is a sub-region of the first region (21) with a decreased electrical conductivity.

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), whereinthe semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and comprises a well region (22), the first region (21) is of a first conductivity type and the well region (22) is of a different, second conductivity type,the well region (22) is separated from the gate electrode (33) by a gate insulator layer (4),the first region (21) is electrically contacted by means of the first electrode (31) which is a source electrode or an emitter electrode,in the first region (21) there is at least one current limiting region (5), andthe at least one current limiting region (5) is of at least one electrically insulating material.

An electrode structure includes a plurality of FLR electrodes, each having, in at least one of four corner portions, an electrode curve portion defined by an inner edge and an outer edge that are circular arcs in plan view. The inner and outer edges of each electrode curve portion have different centers of curvature and different curvatures. For two mutually adjacent electrode curve portions, the relative magnitudes of the curvatures of the inner and outer edges are opposite. Each electrode curve portion thereby includes a region of large width and a region of narrow width between the inner and outer edges. A part of the region of large width in each electrode curve portion is electrically connected to a corresponding FLR through an FLR connection electrode that penetrates an insulating film.

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

A semiconductor device comprises a semiconductor layer structure, a gate pad on the semiconductor layer structure, and a metal gate runner on the semiconductor layer structure. The metal gate runner comprises an inner gate runner that comprises a first inner segment and a second inner segment that interconnect at a first oblique angle.

A semiconductor component has a circuit carrier with a first conductor layer, in which a first conductor path is formed. A first thyristor chip has, on its upper face, an anode contact and a gate contact and, on its lower face, a cathode contact placed for electrical connection on the first conductor path. A second thyristor chip has, on its upper face, a cathode contact and a gate contact and, on its lower face, an anode contact placed for electrical connection on the first conductor path. At least one electrically conductive connection element connects the anode contact of the first thyristor chip to the cathode contact of the second thyristor chip. The first conductor path thus establishes an electrical connection between the cathode contact of the first thyristor chip and the anode contact of the second thyristor chip.

A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.

An apparatus and an associated method for a reverse-conducting insulated gate bipolar transistors and associated structures. The apparatus includes a substrate disposed between a frontside and a backside, a diode pilot region disposed in the substrate, an insulated gate bipolar transistor (IGBT) region disposed in the substrate, and a diode region with a barrier layer disposed adjacent to each of and between the diode pilot region and the IGBT region. The barrier layer is configured to prevent flow of electrons at a first predetermined current and allow flow of electrons at a second predetermined current.

The present invention relates to a semiconductor device including: a semiconductor substrate having: an active region through which a main current flows; and a termination region around the active region; a polyimide film disposed in the active region and the termination region; and a passivation film disposed as a film underlying the polyimide film, wherein the termination region includes, in order from a side of the active region, a breakdown voltage holding region and an outermost peripheral region, the polyimide film is disposed except for a dicing remaining portion of the outermost peripheral region, and the passivation film is disposed, as the underlying film, at least in a region where the polyimide film is disposed.