An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.

There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

A field effect transistor and a semiconductor device including the same are provided. The semiconductor device may include a channel layer, which is provided on a substrate and includes a two-dimensional atomic layer made of a first material, and a source/drain layer, which is provided on the substrate and includes a second material. The first material may be one of phosphorus allotropes, the second material may be one of carbon allotropes, and the channel layer and the source/drain layer may be connected to each other by covalent bonds between the first and second materials.

A method for forming a semiconductor device includes forming a fin device structure in a buffer layer on a substrate. The fin device structure includes a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion. The method also includes forming a sacrificial layer disposed over the fin device structure and forming a device semiconductor layer disposed over a surface of the sacrificial layer. A gate dielectric layer is then formed and is disposed over a surface of the device semiconductor layer. A gate electrode layer is formed and disposed over a surface of the gate dielectric layer. The method includes removing a portion of the sacrificial layer to form a cavity surrounding the fin structure and performing an oxidation process to form a thermal oxide layer in the cavity surrounding the side surface of the fin structure.

Transistors using nitride semiconductor layers as channels were experimentally manufactured. The nitride semiconductor layers were all formed through a sputtering method. A deposition temperature was set at less than 600 C., and a polycrystalline or amorphous In.sub.xGa.sub.yAl.sub.zN layer was obtained. When composition expressed with a general expression In.sub.xGa.sub.yAl.sub.zN (where x+y+z=1.0) falls within a range of 0.3x1.0 and 0z<0.4, a transistor 1a exhibiting an ON/OFF ratio of 10.sup.2 or higher can be obtained. That is, even a polycrystalline or amorphous film exhibits electric characteristics equal to those of a single crystal. Therefore, it is possible to provide a semiconductor device in which constraints to manufacturing conditions are drastically eliminated, and which includes an InGaAlN-based nitride semiconductor layer which is inexpensive and has excellent electric characteristics as a channel.

A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

Provided are an electronic/optical device, which is reduced in contact resistance occurring between a layered material layer and a metal electrode layer, and a method of manufacturing the device. The electronic/optical device of the present invention includes a laminated structure in which an intermediate layer is arranged between a layered material layer (2) and a metal electrode layer (3). The intermediate layer is a crystal layer (4) of an intermediate layer-forming material containing: at least one of Sb and Bi; and Te. In addition, the method of manufacturing an electronic/optical device of the present invention includes: an intermediate layer-forming step of forming, on the layered material layer (2), the intermediate layer (crystal layer (4)) obtained by crystallizing an intermediate layer-forming material containing: at least one of Sb and Bi; and Te; and a metal electrode layer-forming step of forming the metal electrode layer (3) on the intermediate layer.

A transistor includes a channel layer, a gate stack, and source/drain regions. The channel layer includes a graphene layer and hexagonal boron nitride (hBN) flakes dispersed in the graphene layer. Orientations of the hBN flakes are substantially aligned. The gate stack is over the channel layer. The source/drain regions are aside the gate stack.