Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

A heterostructure device includes a channel layer, a barrier layer disposed on the channel layer, and a first electrode and a second electrode disposed on the barrier layer, respectively. The second electrode includes a p-type semiconductor structure and a raised section disposed on the p-type semiconductor structure, the second electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface of the p-type semiconductor structure and a first bottom surface of the raised section, the ohmic contact is formed between a second bottom surface of the raised section and the barrier layer.

The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

A semiconductor device includes: a substrate; a semiconductor stack including a first nitride semiconductor layer and a second nitride semiconductor layer formed above the substrate; a source electrode and a drain electrode formed above a lower surface of the semiconductor stack; a gate electrode; in plan view, a current-drift area; a non-current-drift area; and a collapse reducing electrode formed on the non-current-drift area in the second nitride semiconductor layer, the collapse reducing electrode being formed to have a substantially same potential as the gate electrode. In the semiconductor device, the collapse reducing electrode and the second nitride semiconductor layer have a junction surface functioning as an energy barrier having a rectifying effect in a forward direction from the collapse reducing electrode to the second nitride semiconductor layer.

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

A field effect diode comprises: a substrate; a nucleation layer, a back barrier layer, a channel layer, a first barrier layer and a second barrier layer sequentially located on the substrate; and an anode and a cathode located on the second barrier layer, wherein a groove is formed in the second barrier layer, two-dimensional electron gas is formed at an interface between the first barrier layer and the channel layer except for a part of the interface under the groove when a reverse bias voltage or no external voltage is applied to the field effect diode, and is formed at all parts of the interface when a forward bias voltage is applied to the field effect diode.

This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a N-type field-effect transistor positioned in the semiconductor substrate, and a P-type field-effect transistor positioned in the semiconductor substrate and spaced apart the N-type field-effect transistor. N-type field-effect transistor includes a first germanium nanowire, a first III-V compound layer surrounding around the first germanium nanowire, a first potential barrier layer mounted on the first III-V compound layer, a first gate dielectric layer, a first gate, a first source region and a first drain region mounted on two sides of the first gate. P-type field-effect transistor includes a second germanium nanowire, a second III-V compound layer surrounding around the second germanium nanowire, a second potential barrier layer mounted on the second III-V compound layer, a second gate dielectric layer, a second gate, a second source region and a second drain region mounted on two sides of the second gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and the P-type and N-type field-effect transistors are gate-surrounding devices to enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

A method of forming an active device on a semiconductor wafer includes the steps of: forming a plurality of semiconductor fins on at least a portion of a semiconductor substrate; forming a dielectric layer on at least a portion of the semiconductor substrate, the dielectric layer filling gaps between adjacent fins; forming a plurality of gate structures on an upper surface of the dielectric layer; forming a channel region on the dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material; forming source and drain epitaxy regions on an upper surface of the dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another; and replacing the channel region with a second crystalline semiconductor material after high-temperature processing used in fabricating the active device has been completed.