A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a NMOS active region, a PMOS active region and a shallow trench isolation (STI) region; forming a plurality of first hexagonal epitaxial wires on the NMOS active region and the PMOS active region by selective epitaxially growing a germanium (Ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the NMOS active region by selective epitaxially growing a III-V semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the NMOS active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.

Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of In.sub.x1Al.sub.y1Ga.sub.1x1y1N (0x1<1, 0y1<1, 0<1x1y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of In.sub.x2Al.sub.y2Ga.sub.1x2y2N (0x2<1, 0y2<1, 0<1x2y21) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

A vertical field effect device includes a substrate and a vertical channel including In.sub.xGa.sub.1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.

The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.

A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.