Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

A semiconductor device includes a silicon substrate, a silicon germanium (SiGe) layer including a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion, a first dielectric layer disposed over a side surface of the fin structure and a top surface of the lower portion of the silicon germanium (SiGe) layer, an indium gallium arsenide (InGaAs) layer disposed over a surface of the first dielectric layer, a high k oxide layer disposed over a surface of the InGaAs layer, and a metal layer disposed over a surface of the high k oxide layer. The InGaAs layer includes a source region, a channel region, and a drain region. The metal layer is configured to be a first gate electrode, and the fin structure in the SiGe layer is configured to be a second gate electrode.

In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including Si.sub.xGe.sub.1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.

A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Provided is a two-dimensional large-area growth method for a chalcogen compound, the method including: depositing a film of a transition metal element or a Group V element on a substrate; thereafter, uniformly diffusing a vaporized chalcogen element, a vaporized chalcogen precursor compound or a chalcogen compound represented by MX.sub.2+ within the film; and, thereafter, forming a film of a chalcogen compound represented by MX.sub.2 by forming the chalcogen compound represented by MX.sub.2 through post-heating.

A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.