An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.

The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with AlGaN, and the third semiconductor layer has a lower composition ratio of Al than that of the second semiconductor layer.

A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage.

A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 m.

A thin film transistor, an array substrate and manufacturing method thereof, and a display device are provided. The thin film transistor includes an active layer, a source electrode, a drain electrode, and a first gate electrode, the first gate electrode is shaped in a ring. The active layer includes a first portion, a second portion and a third portion for connecting the first portion and the second portion. The first portion and the second portion are disposed horizontally, and connected to the source electrode and the drain electrode, respectively. The third portion is disposed obliquely, and has a channel provided thereon. At least one part of the channel is located on an inner side of the first gate electrode. The thin film transistor can be used in a display device.

A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Generally discussed herein are techniques for and systems and apparatuses configured to control phonons using an electric field. In one or more embodiments, an apparatus can include electrical contacts, two quantum dots embedded in a semiconductor such that when an electrical bias is applied to the electrical contacts, the electric field produced by the electrical bias is substantially parallel to an axis through the two quantum dots, and a phononic wave guide coupled to the semiconductor, the phononic wave guide configured to transport phonons therethrough.

A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).