An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.

An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.

A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

An antifuse structure includes an active area, a gate electrode and a dielectric layer. The gate electrode is over the active area, in which the gate electrode is ring-shaped, and a portion of the gate electrode is overlapped with a portion of the active area in a vertical projection direction, and the portion of the active area has a dopant concentration higher than a dopant concentration of another portion of the active area. The dielectric layer is sandwiched between the portion of the active area and the portion of the gate electrode.

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.

A memory element according to an embodiment includes: first through fourth impurity layers arranged in a semiconductor layer including first to third portions; a first gate wiring line disposed on the first portion located between the first and second impurity layers; a second gate wiring line disposed on the second portion located between the second and third impurity layers; a third gate wiring line disposed on the third portion located between the third and fourth impurity layers; a first insulating layer disposed between the first portion and the first gate wiring line; a second insulating layer disposed between the second portion and the second gate wiring line; a third insulating layer disposed between the third portion and the third gate wiring line; first wiring line electrically connected to the first through third gate wiring lines; and second wiring line electrically connected to the first through fourth impurity layers.

Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.

A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.