In an embodiment, a III-V nitride semiconductor device comprises an AlGaN epitaxial layer and a metal electrode. The AlGaN epitaxial layer is a C-plane n-type or undoped layer, and the AlGaN epitaxial layer has an epitaxial surface consisting of one or more semi-polar planes. The metal electrode is directly formed on the one or more semi-polar planes.

The invention provides a thin film transistor, an array substrate and a display device. The thin film transistor comprises a conductive oxygen vacancy reducing layer for reducing oxygen vacancies in an active layer. The oxygen vacancy reducing layer is disposed between the active layer and a source and/or the active layer and a drain. With the oxygen vacancy reducing layer, the number of the oxygen vacancies in the active layer is decreased greatly, which improves transmission rate of carriers and simultaneously reduces value of subthreshold swing of the thin film transistor.

The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is generally expressed with C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2) . There are provided a high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, a manufacturing apparatus of such an SiC epitaxial wafer, a fabrication method of such an SiC epitaxial wafer, and a semiconductor device.

A semiconductor device includes: an electron transit layer constituted of GaN; an electron supply layer constituted of In.sub.x1Al.sub.y1Ga.sub.1-x1-y1N (0x1<1, 0y1<1, 0<1x1y1<1) and provided on the electron transit layer; a source electrode and a drain electrode that are provided on the electron supply layer and located apart from each other; a threshold voltage adjustment layer constituted of In.sub.x2Al.sub.y2Ga.sub.1-x2-y2N (0x2<1, 0y2<1, 0<1x2y21) of a p-type and provided on a part of the electron supply layer located between the source electrode and the drain electrode; and a gate electrode provided on the threshold voltage adjustment layer. A high resistance layer is respectively interposed both between the gate electrode and the threshold voltage adjustment layer, and between the threshold voltage adjustment layer and the electron supply layer.

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

A silicon carbide wafer has one surface and the other surface opposite to the one surface. An average Rmax roughness of the one surface is 2.0 nm or less, and an average Ra roughness of the one surface is 0.1 nm or less. An edge region is a region in which a distance from an edge of the silicon carbide wafer toward a center is 5% to 75% of a radius of the silicon carbide wafer, and a central region is a region having a radius of 25% of the radius of the silicon carbide wafer at the center of the silicon carbide wafer. A difference between an average Rmax roughness of the edge region of the one surface and an average Rmax roughness of the central region of the one surface is 0.01 nm to 0.5 nm.

In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface and at least one transistor device structure, a source pad and a gate pad arranged on the first major surface, a drain pad and at least one further contact pad coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0.