A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Provided a semiconductor device. The semiconductor device comprises an active pattern extending in a first direction on a substrate, a gate stack extending in a second direction intersecting the first direction on the active pattern, and a source/drain pattern on at least one side of the gate stack, wherein the gate stack includes a first work function pattern, a second work function pattern on the first work function pattern, and a diffusion prevention pattern between the first work function pattern and the second work function pattern, and wherein a concentration of aluminum in the second work function pattern is greater than a concentration of aluminum in the first work function pattern.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first metal gate stack and a second metal gate stack over the substrate and the first dielectric layer. The semiconductor device structure further includes a second dielectric layer beside the first metal gate stack and an insulating structure over the substrate. A portion of the insulating structure is between the first metal gate stack and the second metal gate stack. The insulating structure penetrates into the second dielectric layer.

Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

An IC structure includes a plurality of first channel regions and a plurality of second channel regions over a substrate, a plurality of first gate structures traversing the plurality of first channel regions, and a plurality of second gate structures traversing the plurality of second channel regions. The first gate structures have a first gate pitch. The second gate structures have a second gate pitch different than the first gate pitch. The IC structure further includes first gate contact over a first one of the second gate structures. The first gate contact overlaps a location where the first one of the second gate structures traverses across a first one of the second channel regions. The first gate contact further overlaps a location where the first one of the second gate structures traverses across a second one of the second channel regions.

A semiconductor device includes: a substrate including a first active pattern and a second active pattern which are spaced apart from each other; a first gate structure disposed on the first active pattern; a second gate structure disposed on the second active pattern; and a channel semiconductor pattern disposed between the second active pattern and the second gate structure, wherein the first gate structure includes: a first insulating pattern, a second insulating pattern and a first high-k dielectric pattern, which are stacked on the first active pattern, wherein the second gate structure includes: a third insulating pattern and a second high-k dielectric pattern, which are stacked on the channel semiconductor pattern, and wherein a thickness of the third insulating pattern ranges from 12 to 13 .

Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

A wimpy finFET device and method for fabricating the same is described. The device is fabricated by forming a mandrel that is non-perpendicular to long axes of the underlying fin(s) (i.e., the mandrel is formed at a non-quadrantal angle with respect to the long axes). Spacers formed on the sidewalls of the angled mandrel are thus also formed non-perpendicular to the long axes. The spacers are used to pattern underlying layer(s) down to the underlying fin(s) to form the gates for the device. Because the patterned layer(s) are also formed at a non-quadrantal angle, the width of the patterned layer(s) over the underlying fin(s) is greater than would be if the patterned layer(s) were formed at, e.g., a right angle with respect to the long axis. The desired gate length and gate pitch is respectively achieved by determining the angle at which the mandrel is formed and the mandrel width.

Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate.

An integrated circuit including a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, and a body region. The source region includes an outer region having a first conductivity type complementary to a second conductivity type of an outer region of the body and an interior-positioned conductive region having the second conductivity type.