A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.

A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (V.sub.t) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.

The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V.sub.dd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V.sub.th) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V.sub.ss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.

An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.

A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.

An SRAM memory device includes a substrate, a first transistor, a second transistor, a metal interconnect structure, and a capacitor. The metal interconnect structure is formed on the first and second transistors. The capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The lower metal layer is coupled to a source node of the first transistor and a source node of the second transistor. The lower metal layer and an n-th metal layer in the metal interconnect structure are formed of a same material, wherein n≥1; the upper metal layer and an m-th metal layer in the metal interconnect structure are formed of a same material, wherein m≥n+1.

A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.