H10F39/812

Metal-contact-free photodetector

A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at 4 V reverse bias. 3-dB bandwidth is 30 GHz.

PIXEL CIRCUIT

A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.

CMOS image sensors including vertical transistor

Provided is a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can include a substrate having a first device isolation layer defining and dividing a first active region and a second active region, a photodiode disposed in the substrate and can be configured to vertically overlap the first device isolation layer, a transfer gate electrode can be disposed in the first active region and can be configured to vertically overlap the photodiode, and a floating diffusion region can be in the first active region. The transfer gate electrode can be buried in the substrate.

Insulating wall and method of manufacturing the same
09793312 · 2017-10-17 · ·

A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS
20170287982 · 2017-10-05 ·

Provided is a solid-state image pickup device that makes it possible to enhance image quality, and a manufacturing method thereof, and an electronic apparatus. A solid-state image pickup device includes a pixel section that includes a plurality of pixels, the pixels each including one or more organic photoelectric conversion sections, wherein the pixel section includes an effective pixel region and an optical black region, and the organic photoelectric conversion sections of the optical black region include a light-shielding film and a buffer film on a light-incidence side.

Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
09763566 · 2017-09-19 · ·

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

Solid-state imaging device and imaging apparatus
09762867 · 2017-09-12 · ·

The present technique relates to a solid-state imaging device and an imaging apparatus that enable provision of a solid-state imaging device having superior color separation and high sensitivity. The solid-state imaging device includes a semiconductor layer 11 in which a surface side becomes a circuit formation surface, photoelectric conversion units PD1 and PD2 of two layers or more that are stacked and formed in the semiconductor layer 11, and a longitudinal transistor Tr1 in which a gate electrode 21 is formed to be embedded in the semiconductor layer 11 from a surface 15 of the semiconductor layer 11. The photoelectric conversion unit PD1 of one layer in the photoelectric conversion units of the two layers or more is formed over a portion 21A of the gate electrode 21 of the longitudinal transistor Tr1 embedded in the semiconductor substrate 11 and is connected to a channel formed by the longitudinal transistor Tr1.

SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS
20170250210 · 2017-08-31 ·

Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.

SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE, AND ELECTRONIC APPARATUS
20170243906 · 2017-08-24 ·

There is provided a solid-state image pickup device including: a semiconductor substrate; a photodiode formed in the semiconductor substrate; a transistor having a gate electrode part or all of which is embedded in the semiconductor substrate, the transistor being configured to read a signal electric charge from the photodiode via the gate electrode; and an electric charge transfer layer provided between the gate electrode and the photodiode.

Photosensitive capacitor pixel for image sensor

A method of fabricating a pixel array includes forming a transistor network along a frontside of a semiconductor substrate. A contact element is formed for every pixel in the pixel array that is electrically coupled to a transistor within the transistor network. An interconnect layer is formed upon the frontside to control the transistor network with a dielectric that covers the contact element. A cavity is formed in the interconnect layer. A conductive layer is formed along cavity walls of the cavity and a dielectric layer is formed over the conductive layer within the cavity. A photosensitive semiconductor material is deposited over the dielectric layer within the cavity. An electrode cavity is formed that extends into the contact element. The electrode cavity is at least partially filled with a conductive material to form an electrode. The electrode, the conductive layer, and the photosensitive semiconductor material form a photosensitive capacitor.