A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

A chip package, a chip package system, a method of manufacturing a chip package, and a method of operating a chip package including: a first sensor configured to measure a magnetic field component up to a maximum magnetic field value; a second sensor configured to measure the magnetic field component beyond the maximum magnetic field value; and a circuit coupled to the first sensor and the second sensor and configured to receive at least one sensor signal from at least one of the first sensor and the second sensor, wherein the circuit is further configured to select the first sensor or the second sensor to measure the magnetic field component based on the received sensor signal.

Devices and methods for forming a device are disclosed. A substrate having circuit component formed on a substrate surface is provided. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A pair of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.

Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element including material layers over a substrate; forming a hard mask layer including a metal over the material layers; selectively etching the hard mask layer to form an etched hard mask layer; etching the material layers by using the etched hard mask layer as an etch barrier, the etching of the material layers providing an etch byproduct formed on sidewalls of the etched material layers and the etch byproduct including a material that is more readily oxidized than the metal of the hard mask layer; and performing a treatment using a gas or plasma to suppresses oxidation of the hard mask layer and facilitate oxidation of the etch byproducts.

A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. The seed layer includes first and second seed layer separated by a surface smoother, such as a surfactant layer. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

Provided is a structure having a perpendicular magnetization film which is an (Mn.sub.1-xGa.sub.x).sub.4N.sub.1-y (0<x≦0.5, 0<y<1) thin film having a nitrogen-deficient composition which is formed by controlling and introducing nitrogen N into an MnGa alloy or a thin film containing at least one of Ge, Zn, Sb, Ni, Ag, Sn, Pt, and Rh, instead of Ga. The perpendicular magnetization film exhibits a Curie temperature sufficiently higher than room temperature, has saturation magnetization smaller than that of existing materials, and is capable of being fabricated as a very flat film.

A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a first heavy metal layer and a first magnetic tunnel junctions (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area that is different than the first area. The second MTJ shared a reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer that is coupled to the second MTJ.

A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.