Encapsulation of the magnetoresistive device after formation protects the sidewalls of the magnetoresistive device from degradation during subsequent deposition of interlayer dielectric material. The encapsulation also helps prevent short circuits between the top electrode of the magnetoresistive device and underlying layers within the magnetoresistive device. The encapsulation can be accomplished by depositing a layer of encapsulating material after device formation, where an etch back operation selectively removes the portions of the layer of encapsulating material other than the material on the sidewalls of the magnetoresistive device.

A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

A method of fabricating a semiconductor device includes aligning an alignment structure of a wafer to a direction of a magnetic field created by an external electromagnet and depositing a magnetic layer (e.g., NiFe) over the wafer in the presence of the magnetic field and while applying the magnetic field and maintaining a temperature of the wafer below 150° C. An insulation layer (e.g., AlN) is deposited on the first magnetic layer. The alignment structure of the wafer is again aligned to the direction of the magnetic field and a second magnetic layer is deposited on the insulation layer, in the presence of the magnetic field and while maintaining the temperature of the wafer below 150° C.

A method of manufacturing a magnetoresistive device according to an embodiment includes: forming an underlying film including silicon, oxygen, and carbon, on a substrate; performing plasma ashing on the underlying film by using plasma of an oxygen-containing gas; forming a multilayer film including a metal layer and a magnetic layer, on the underlying film subjected to ashing; and performing plasma etching on the multilayer film by using plasma of a hydrogen-containing gas.

In some embodiments, the present disclosure relates to a method to form an integrated chip. The method may be performed by forming magnetic tunnel junction (MTJ) layers over a bottom electrode layer, and forming a sacrificial dielectric layer over the MTJ layers. The sacrificial dielectric layer is patterned to define a cavity, and a top electrode material is formed within the cavity. The sacrificial dielectric layer is removed and the MTJ layers are patterned according to the top electrode material to define an MTJ stack, after removing the sacrificial dielectric layer.

A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.

A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a memory cell stack over a substrate. The memory cell stack comprises a tunnel barrier layer, a free layer over the tunnel barrier layer, a capping dielectric layer over the free layer, and a conductive capping layer on the capping dielectric layer. A conductive shunting structure is formed along outer sidewalls of the free layer, outer sidewalls of the capping dielectric layer, and outer sidewalls of the conductive capping layer. A bottommost point of the conductive shunting structure in contact with the free layer is disposed above a bottom surface of the free layer.