Patent classifications
H01L43/12
ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE
An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
METHODS AND APPARATUSES FOR PRODUCING MAGNETORESISTIVE APPARATUSES
Methods and apparatuses for producing magnetoresistive apparatuses are provided. Here, structures are formed for defining regions of the same magnetization, magnets are magnetized, and structures are formed within the magnets of the regions, for example, in order to define magnetoresistive elements.
FABRICATING A CAP LAYER FOR A MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE
A method for manufacturing a semiconductor device includes forming a magnetic tunnel junction (MTJ) structure comprising a magnetic fixed layer, a non-magnetic barrier layer and a magnetic free layer, and forming a metal oxide cap layer on the MTJ structure, wherein forming the metal oxide cap layer comprises depositing a metal layer on the magnetic free layer, performing an oxidation of the deposited metal layer to form an oxidized metal layer, and depositing a metal oxide layer on the oxidized metal layer.
METHODS FOR ADDITIVE FORMATION OF A STT MRAM STACK
Disclosed herein are methods for additive formation of a STT-MRAM metal stack using a deposition process through a pre-patterned template that skims away metal ions that are less likely to enable anisotropic deposition on a substrate. The pre-patterned template is formed from a film stack using patterning techniques to form an opening in the film stack that exposes portions of an underlying substrate where a MTJ will be formed for an MRAM cell. The film stack cavity may be exposed to etch processes that selectively pull back the sidewall, such that other layers in the film stack protrude into the cavity. Additional treatments to the other layers may alter the opening sizes in the other layers. Metal deposited through the cavity such that metal ions with anisotropic characteristics will be skimmed away before reaching the substrate.
Magnetic tunnel junction (MTJ) device and manufacturing method thereof
A magnetic tunnel junction (MTJ) device includes at least one magnetic tunnel junction element, silicon nitride spacers and tantalum containing spacers. The magnetic tunnel junction element is disposed on a dielectric layer, wherein a corresponding metal line is disposed in the dielectric layer contacting to the magnetic tunnel junction element. The silicon nitride spacers are disposed on sidewalls of the magnetic tunnel junction element. The tantalum containing spacers are disposed on sidewalls of the silicon nitride spacers, wherein at least one of the tantalum containing spacers includes a top part covering a part of a top surface of the magnetic tunnel junction element. The present invention also provides a method of manufacturing said magnetic tunnel junction (MTJ) device.
Dual-Axis Fluxgate Device
A fluxgate device that includes a first magnetic core and a second magnetic core. The first magnetic core has a first magnetized direction that deviates from a first sense direction by more than 0 degree and less than 90 degrees. The second magnetic core is arranged orthogonally to the first magnetic core. The second magnetic core has a second magnetized direction that deviates from a second sense direction by more than 0 degree and less than 90 degrees.
PERPENDICULAR MAGNETIC LAYER AND MAGNETIC DEVICE INCLUDING THE SAME
Embodiments of the inventive concepts provide a flat perpendicular magnetic layer having a low saturation magnetization and a perpendicular magnetization-type tunnel magnetoresistive element using the same. The perpendicular magnetic layer is a nitrogen-poor (Mn.sub.1−xGa.sub.x)N.sub.y layer (0<x≦0.5 and 0<y<0.1) formed by providing nitrogen (N) into a MnGa alloy while adjusting a nitrogen amount. The perpendicular magnetic layer can be formed flat.
Post Treatment to Reduce Shunting Devices for Physical Etching Process
A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
SEMICONDUCTOR DEVICE INCLUDING VIA PLUGS
A semiconductor device includes a lower insulating layer on a substrate, a lower wiring layer extending on the lower insulating layer, a lower surface of at least a part of the lower wiring layer being covered by the lower insulating layer, a plurality of via plugs extending in a first direction on the lower wiring layer, the plurality of via plugs including a real via plug and a first dummy via plug connected to the part of the lower wiring layer covered by the lower insulating layer, and an upper wiring layer overlapping the lower wiring layer and extending in a second direction different from the first direction on the real via plug, the upper wiring layer not overlapping the dummy via plug.
SOT-MRAM CELL IN HIGH DENSITY APPLICATIONS
In some embodiments, the present disclosure relates to a memory device that includes a spin orbit torque (SOT) layer arranged over a substrate. A magnetic tunnel junction (MTJ) structure may be arranged over the SOT layer. The MTJ structure includes a free layer, a reference layer, and a diffusion barrier layer disposed between the free layer and the reference layer. A first conductive wire is arranged below the SOT layer and coupled to the SOT layer. A second conductive wire is arranged below the SOT layer and coupled to the SOT layer. A third conductive wire is arranged over the MTJ structure. The memory device further includes a first selector structure arranged between the first conductive wire and the SOT layer.