Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state. The device is configured such that the switching loss is different between at least two of the zones. Further, the device is configured such that zones having greater switching losses transition to the non-conducting state before zones having lesser switching losses.

A method for fabricating a complementary bipolar junction transistor (BJT) integrated structure. The method includes forming a first backplate in a monolithic substrate below a first buried oxide (BOX) layer. Another forming step forms a second backplate in the monolithic substrate below the first BOX layer. The second backplate is electrically isolated from the first backplate. Another forming step forms an NPN lateral BJT above the first BOX layer and superposing the first backplate. The NPN lateral BJT is configured to conduct electricity horizontally between an NPN emitter and an NPN collector when the NPN lateral BJT is active. Another forming step forms a PNP lateral BJT superposing the second backplate. The PNP lateral BJT is configured to conduct electricity horizontally between a PNP emitter and a PNP collector when the PNP lateral BJT is active.

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.

A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact to the base.

A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

Structures including an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate having a top surface, an electrostatic discharge protection device including a base in the semiconductor substrate, and first and second trench isolation regions disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth greater than the first depth.

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.

A complementary bipolar junction transistor (BJT) integrated structure and methods for fabricating and operating such. The structure includes a monolithic substrate and conductive first and second backplates electrically isolated from each other. An NPN lateral BJT is superposed over the first backplate, and a PNP lateral BJT is superposed over the second backplate. A buried oxide (BOX) layer is positioned between the NPN lateral BJT and the first backplate, and between the PNP lateral BJT and the second backplate.