The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

An integrated circuit (IC) device includes a semiconductor substrate and a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region, the collector region formed in or over the semiconductor substrate, the base region disposed between the collector region and the emitter region, the base region comprising a heteroepitaxial portion including a narrow band of an n-dopant region.

An electronic device includes an NPN bipolar transistor in an isolation tank region of an n-type semiconductor layer and having a p-type base region, an n-type emitter region, and an n-type collector region and a PNP bipolar transistor in the isolation tank region of the semiconductor layer and having an n-type base formed by a portion of the n-type semiconductor layer, a p-type emitter formed by a portion of the p-type base region of the NPN bipolar transistor, and a p-type collector formed by a p-type second collector region in the isolation tank region of the semiconductor layer and spaced apart from the p-type base region and from the n-type collector region of the NPN bipolar transistor.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.

An IGBT device includes an p-type collector region, an n-type semiconductor layer, several p-type body regions located in the n-type semiconductor layer, a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a gate trench located in the n-type semiconductor layer and between adjacent p-type body regions, a shielded gate located in a lower part of the gate trench, and a gate located in an upper part of the gate trench. The gate, the shielded gate, and the n-type semiconductor layer are insulated and isolated from each other. Among the several p-type body regions, at least one p-type body region has a first doping concentration and is defined as a first p-type body region, and at least one p-type body region has a second doping concentration and is defined as a second p-type body region.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

An electrostatic discharge semiconductor device and a manufacturing method thereof are disclosed. The electrostatic discharge semiconductor device includes: a substrate, an epitaxial layer and a first well region; a second well region and a third well region located on sides of the first well region respectively; a fourth well region extending in the first well region; fifth and sixth well regions on sides of the fourth well region; a first injection region and a second injection region. The second injection region in the second well region and third well region, and the first injection region in the fifth well region and sixth well region are connected to a cathode, and all injection regions in the fourth well region are connected to an anode, to form a lateral triode current discharge path, which increases the holding voltage and adjusts the avalanche breakdown voltage and trigger voltage, and enhances electrostatic protection capability.

An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.