A highly reliable semiconductor device with favorable electrical characteristics is provided. A semiconductor device includes a semiconductor layer, an insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the insulating layer, the metal oxide layer, and the conductive layer are stacked in this order. The semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer. The second regions sandwich the first region, overlap the insulating layer, and do not overlap the metal oxide layer. The third regions sandwich the first region and the pair of second regions, and do not overlap the insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.

A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 m to about 2 m, and a length of the channel of the third transistor is in a range of about 1 m to about 2.5 m.

A thin film transistor array substrate includes a glass substrate and a plurality of TFTs thereon. Each TFT includes a gate formed on the glass substrate, a gate insulating layer covering the gate, an active layer formed on the gate insulating layer, a source on the active layer, and a drain on the active layer. A gap is between the source and the drain in a first direction. An area of the active layer that matches the gap is a channel. A plurality of protrusions and recesses on a coarse surface of the gate insulating layer face the active layer, at least within the area corresponding to the channel. The active layer fits with the gate insulting layer. The present invention also proposes a method for manufacturing the thin film transistor array substrate and a liquid crystal display panel having the thin film transistor array substrate.

A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.

An array substrate and a manufacturing method thereof, a display device and a thin film transistor are provided. The method includes forming a pattern that includes an active layer, a pixel electrode and a data line on a base substrate; forming a pattern that includes a gate insulating layer and at least two gate via-holes therein, the at least two gate via-holes are located in regions in the gate insulating layer that correspond to outer surroundings of the active layer and do not overlap with areas where the pixel electrode and the data line are located; forming a pattern that includes a gate line and at least two gate electrodes, the at least two gate electrodes are connected to the gate line, and are provided in the at least two gate via-holes, respectively. With this method, the fabricating process and the fabricating cost are saved.

A thin film transistor, an array substrate and a liquid crystal display panel are provided. The thin film transistor has an active layer which is formed from nitrogen-doped oxide semiconductor layers and a non-nitrogen doped oxide semiconductor layer. By disposing the non-nitrogen doped oxide semiconductor layer in the active layer of the nitrogen-doped thin film transistor, the mobility of the thin film transistor is kept constant for improving the reliability of the thin film transistor.

The present invention provides a transistor and a fabrication method thereof. By a silicon nanowire as a core region being serially wrapped by a germanium channel, a gate insulating film and a gate, the present invention enables to form a potential well for storing holes as a carrier of HHMT in the germanium channel by a valance band energy offset between the silicon core region and the germanium channel, to gain maximum gate controllability to the germanium channel, and to simplify a fabricating process by simultaneously forming the germanium channel and the gate insulating film in one process.

Disclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a source electrode and a drain electrode formed on the semiconductor layer and the gate insulating layer and facing each other; and a pixel electrode connected to the drain electrode and applied with a voltage from the drain electrode, wherein a thickness of the gate insulating layer which overlaps the drain electrode but does not overlap the semiconductor layer is formed to be thinner than that which overlaps the semiconductor.

A transistor includes a gate electrode, an oxide semiconductor film, and a gate insulating film. The oxide semiconductor film includes a channel region and a low-resistance region. The channel region faces the gate electrode. The low-resistance region has a resistance value lower than a resistance value of the channel region. The gate insulating film is provided between the oxide semiconductor film and the gate electrode, and has a first surface located closer to the oxide semiconductor film and a second surface located closer to the gate electrode. The first surface of the gate insulating film has a length in a channel length direction which is greater than a maximum length of the gate electrode in the channel length direction.

A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.