TRANSISTOR HAVING GERMANIUM CHANNEL ON SILICON NANOWIRE AND FABRICATION METHOD THEREOF

Abstract

The present invention provides a transistor and a fabrication method thereof. By a silicon nanowire as a core region being serially wrapped by a germanium channel, a gate insulating film and a gate, the present invention enables to form a potential well for storing holes as a carrier of HHMT in the germanium channel by a valance band energy offset between the silicon core region and the germanium channel, to gain maximum gate controllability to the germanium channel, and to simplify a fabricating process by simultaneously forming the germanium channel and the gate insulating film in one process.

Claims

1. A transistor comprising: a silicon nanowire; an active region wrapped around the silicon nanowire; a gate insulating film wrapped around the active region; and a gate wrapped around the gate insulating film, wherein the active region is formed of germanium and/or silicon germanium and the gate insulating film is a silicon oxide film.

2. The transistor of claim 1, wherein source and drain electrodes are separately wrapped around the active region at both sides of the gate.

3. The transistor of claim 2, wherein source and drain regions are formed in the active region wrapped by the source and drain electrodes, respectively and wherein a body or channel region is formed in the other region of the active region except the source/drain regions.

4. The transistor of claim 3, wherein the source and drain regions are doped with a p-type impurity having a concentration of 10.sup.1610/cm.sup.3 and the channel region is undoped or doped with an n-type impurity having a concentration of 10.sup.18/cm.sup.3 or lower.

5. The transistor of claim 1, wherein source and drain electrodes are separately formed at both ends of the active region.

6. The transistor of claim 5, wherein source and drain regions are separately formed at both ends of the active region and the source and drain electrodes are formed on the source and drain regions, respectively.

7. The transistor of claim 6, wherein source and drain regions are doped with a p-type impurity having a concentration of 10.sup.1610.sup.20/cm.sup.3 and the channel region is undoped or doped with an n-type impurity having a concentration of 10.sup.18/cm.sup.3 or lower.

8. The transistor of claim 1, wherein the active region, the gate insulating film and the gate are coaxially and cylindrically wrapped around the silicon nanowire, respectively.

9. The transistor of claim 8, wherein the active region is formed of germanium or silicon germanium (Si.sub.1-xGe.sub.x, x0.2) with a thickness of 15 nm.

10. The transistor of claim 8, wherein the active region comprises a silicon germanium layer wrapped around the silicon nanowire and a germanium layer wrapped around the silicon germanium layer.

11. The transistor of claim 10, wherein a thickness of the germanium layer is 15 nm.

12. The transistor of claim 2, wherein the active region, the gate insulating film and the gate are coaxially and cylindrically wrapped around the silicon nanowire, respectively.

13. The transistor of claim 12, wherein the active region comprises a silicon germanium layer wrapped around the silicon nanowire and a germanium layer wrapped around the silicon germanium layer.

14. The transistor of claim 3, wherein the active region, the gate insulating film and the gate are coaxially and cylindrically wrapped around the silicon nanowire, respectively.

15. The transistor of claim 14, wherein the active region comprises a silicon germanium layer wrapped around the silicon nanowire and a germanium layer wrapped around the silicon germanium layer.

16. The transistor of claim 5, wherein the active region, the gate insulating film and the gate are coaxially and cylindrically wrapped around the silicon nanowire, respectively.

17. The transistor of claim 16, wherein the active region comprises a silicon germanium layer wrapped around the silicon nanowire and a germanium layer wrapped around the silicon germanium layer.

18. The transistor of claim 6, wherein the active region, the gate insulating film and the gate are coaxially and cylindrically wrapped around the silicon nanowire, respectively.

19. The transistor of claim 18, wherein the active region comprises a silicon germanium layer wrapped around the silicon nanowire and a germanium layer wrapped around the silicon germanium layer.

20. The transistor of claim 19, wherein a thickness of the germanium layer is 15 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a perspective view of a transistor structure according to an embodiment of the present invention.

[0027] FIG. 2 is a cross-sectional view taken along the x-direction in the gate of FIG. 1.

[0028] FIG. 3 is a cross-sectional view taken along the y-direction in the gate of FIG. 1.

[0029] FIG. 4 is a quarter cross-sectional and perspective view of a transistor structure according to another embodiment of the present invention.

[0030] FIG. 5 is a partial cross-sectional view shown in FIG. 4.

[0031] FIG. 6 is a partial cross-sectional view of a transistor structure according to another embodiment of the present invention.

[0032] FIGS. 7A to 7C show an energy band diagram (FIG. 7B) and a hole-current-density diagram (FIG. 7C) in a cross-sectional view (FIG. 7A) of FIG. 3, respectively, when turning-on a transistor of FIG. 1 by applying a negative voltage to a gate.

[0033] FIG. 8 is an electrical characteristic view showing comparison of drain current (b) vs. gate voltage (VGs), when changing a radius of a silicon nanowire and a thickness of a germanium layer in a transistor structure according to an embodiment of FIG. 4.

[0034] FIG. 9 is a simulation result view for measuring a hole concentration in a germanium layer, when a radius of a silicon nanowire and a thickness of a germanium layer are 10 nm, respectively and a negative voltage is applied to a gate.

[0035] FIGS. 10 to 14 are fabricating process diagrams showing a fabrication method for a transistor according to an embodiment of FIG. 4.

[0036] FIGS. 15 and 16 are fabricating process diagrams showing a fabrication method for a transistor according to another embodiment of the present invention.

[0037] In these drawings, the following reference numbers are used throughout: reference number 10 indicates a silicon nanowire, 20 a silicon germanium layer, 30 and 30 an active region or a germanium layer, 40 a silicon oxide film, 42 a gate insulating film or a silicon oxide film, 44 a trench, 50 a gate, 60 a source electrode, 62 a source region, 70 a drain electrode and 72 a drain region.

DETAILED DESCRIPTION

[0038] Detailed descriptions of preferred embodiments of the present invention are provided below with reference to accompanying drawings.

[0039] A transistor according to the present invention, as commonly shown in FIGS. 1 to 6, 14 and 16, comprises: a silicon nanowire 10; an active region 30 and 30 wrapped around the silicon nanowire; a gate insulating film 40 wrapped around the active region; and a gate 50 wrapped around the gate insulating film, wherein the active region 30 and 30 is formed of germanium and/or silicon germanium and the gate insulating film 40 is a silicon oxide film.

[0040] Here, the silicon nanowire 10 can be a silicon rod in a form of a circular column with a diameter of several tens nm or less, the cross-sectional shape of the silicon nanowire 10 can be a circle, an oval, or a polygon like a quadrangle but not limited to. The silicon nanowire 10 can be fabricated by the techniques described in Korean Patent No. 10-0904588, etc.

[0041] The active region 30 and 30 may comprise a channel region forming a channel between source/drain electrodes 60 and 70 and further comprise regions being directly contacted by source/drain electrodes 60 and 70 as shown in FIGS. 1 and 3 or source/drain regions 62 and 72 doped with an impurity to have a high concentration as shown in FIG. 4.

[0042] As described above, because the active region 30 and 30 is a region used directly to operate a transistor, for the objective of the present invention, the active region 30 and 30 is formed to be wrapped around the silicon nanowire 10 with germanium and/or silicon germanium.

[0043] According to the detailed embodiment, the active region 30 and 30 can be a single semiconductor layer 30 formed of germanium or silicon germanium as shown in FIGS. 1 to 6 and 14 or can consist of a silicon germanium layer 20 wrapped around the silicon nanowire 10 and a germanium layer 30 wrapped around the silicon germanium layer 20 as shown in FIG. 16.

[0044] In the former embodiment, it is preferable that the single germanium layer 30 is wrapped around the silicon nanowire 10 of the inside core region in order that a valance band offset (Ev) between the germanium layer 30 as an active region and the silicon nanowire 10 is greatly increased as shown in FIG. 7B.

[0045] The energy bandgaps of germanium and silicon are 0.66 eV and 1.12 eV, respectively. Because the electron affinities of germanium and silicon are similar to each other, the energy bandgap difference between germanium and silicon is almost reflected in the valance band offset.

[0046] Accordingly, as shown in FIG. 7A, when the germanium layer 30 as the active region is wrapped around the silicon nanowire 10, the active region 30 can be formed of a ring-shaped potential well between the silicon nanowire 10 and the silicon oxide film 40 as shown in FIG. 7B and when turning-on the gate by applying a negative voltage, the holes can be collected and confined in the ring-shaped potential well as shown in FIG. 7C. Thus, nanowire transistor can be operated by high hole mobility.

[0047] In the described above, the active region 30 and 30, the gate insulating film 40 and the gate 50 can cover a part of each lower component, respectively, though it is not shown in the accompanying drawings. But it is preferable that the active region 30 and 30, the gate insulating film 40 and the gate 50 are formed to fully cover each lower component as shown in FIGS. 1 to 6, 14 and 16 in order to gain maximum gate controllability to the germanium channel.

[0048] FIG. 8 is an electrical characteristic view showing comparison of drain current (b) vs. gate voltage (VGs) when changing a radius of a silicon nanowire 10 and a thickness of a germanium layer 30 in a transistor structure according to an embodiment of FIG. 4.

[0049] According to FIG. 8, it is shown that the structure of FIGS. 8B and 8C having a silicon nanowire 10 as a core region wrapped by a germanium layer 30 with a predetermined thickness (t) can raise a current drivability more than the structure of FIG. 8A formed of only a germanium layer without the core region of the silicon nanowire 10. As described above, because the ring-shaped potential well can be formed in the germanium layer 30 wrapped around the core region of the silicon nanowire 10 between the silicon nanowire 10 and the silicon oxide film 40 and holes can be collected in the well, it is analyzed that the hole mobility is increased.

[0050] FIG. 9 is a simulation result view for measuring a hole concentration in a germanium layer, when a radius of a silicon nanowire 10 and a thickness (t) of a germanium layer 30 are 10 nm, respectively and a negative voltage is applied to a gate.

[0051] According to FIG. 9, it is known that the concentration of holes as a large number of carriers is maximized at a place (d1) with a distance of about 1 nm from the interface between a silicon oxide film 42 as a gate insulating film and a germanium layer 30. This is caused by a quantum-mechanical effect in the potential well formed in the germanium layer 30 wrapped around the silicon nanowire 10. Thus, the present invention use it to increase a hole mobility for driving SIT.

[0052] When holes are accumulated in the potential well, a channel is formed in the germanium layer 30 under the silicon oxide film 42. The channel 32, as shown in FIG. 9, is formed to be expanded to a predetermined length (d2) from both sides of the gate 50.

[0053] Thus, source and drain electrodes 60 and 70 of a transistor according to the present invention, as shown in FIGS. 1 and 3, can be just wrapped around an active region 30 at both sides of a gate 50. In this case, it can be formed at a distance (d2) of 510 nm from both sides of the gate 50.

[0054] But, more preferably, though it is not shown in drawings, source and drain regions are formed in the portions of the active region wrapped by source and drain electrodes 60 and 70 and a body or channel region can be formed in the other region of the active region except the source/drain regions.

[0055] And because a transistor according to the present invention can have a germanium based pMOSFET structure, the active region can comprise a source region, a channel region and a drain region doped with P+/N/P+, respectively. At this time, preferably, the source and drain regions are doped with a p-type impurity and have a concentration of 10.sup.1610/cm.sup.3 and the channel region is undoped or doped with an n-type impurity and has a concentration of 10.sup.18/cm.sup.3 or lower. If the impurity concentrations of the source and drain regions are much lower than the range, ON/OFF ratio is dropped down due to the very low level of driving current. If the concentration is higher than the range, a leakage current is increased at a turn-off state (i.e., when a positive voltage is applied to the gate). If the impurity concentration of the channel region is over 10.sup.18/cm.sup.3, the leakage current can be increased in the junctions with source and drain regions.

[0056] In another embodiment, as shown in FIG. 6, the source and drain electrodes 60 and 70 can be formed just at both ends of the active region 30.

[0057] In other embodiments, as shown in FIGS. 4, 5, 14 and 16, the source and drain regions 62 and 72 can be firstly formed at both ends of the active region 30 and then the source and drain electrodes 60 and 70 can be formed on the source and drain regions, respectively. In this case, for the same reason as in the above embodiment, it is preferable that the source and drain regions are doped with a p-type impurity having a concentration of 10.sup.1610.sup.20/cm.sup.3 and the channel region is undoped or doped with an n-type impurity having a concentration of 10.sup.18/cm.sup.3 or lower.

[0058] From the simulation result shown in FIG. 9, in each of the embodiments, the active region 30 and 30 is preferably formed of germanium or silicon germanium (Si.sub.1-xGe.sub.x, x0.2) with a thickness (t) of 15 nm. In the latter, if the content of germanium is 20% or less, it is difficult to achieve the objective of the present invention, namely, it has difficulties in forming the potential well and catching efficiently holes by the well.

[0059] In another embodiment, as an embodiment shown in FIG. 16, the active region 30 can comprise a silicon germanium layer 20 wrapped around the silicon nanowire 10 and a germanium layer 30 wrapped around the silicon germanium layer 20. In this case, the thickness of the germanium layer 30 is preferably 15 nm.

[0060] In the above described embodiments, the thickness of the active region formed of germanium or silicon germanium or the thickness of the germanium layer 30 can be limited to 15 nm. If the thickness is 1 nm or less, it is advantageous to raise a controllability of the gate 50 and to suppress a short channel effect, but it has a problem that reduces the total amount of current. If the thickness is over 5 nm, it has a problem that reverses the miniaturization of device because the active region 30 and 30 is unnecessarily enlarged in a state that already obtains enough high-current level of a turn-on state.

[0061] Next, detailed descriptions of a fabrication method of a transistor according to the present invention are provided with reference to FIGS. 10 to 16. Here, FIGS. 10 to 16 are partial cross-sectional views showing a view when a quarter is sectioned as shown in FIG. 4. Accordingly, a whole solid structure can be obtained when the lower end line of each drawing is used as its axis and is rotated by 360 degree.

[0062] First, as shown in FIG. 10, a silicon nanowire 10 may be prepared in a first step and a silicon germanium layer 20 may be wrapped around the silicon nanowire 10 in a second step. Here, the silicon nanowire 10 can be fabricated by the above Korean Patent No. 10-0904588, etc. and the fabrication of the silicon germanium layer 20 can be formed by the known epitaxial crystalline growth or deposition process.

[0063] Next, as shown in FIG. 11, a silicon oxide film 40 can be formed by bonding oxygen to silicon of the silicon germanium layer through an oxidation process for oxidizing the silicon germanium layer 20 and, at the same time, an active region 30 can be formed by condensing germanium into the empty sites of silicon in the silicon germanium layer in a third step. Here, by controlling the conditions of the oxidation process, as shown in FIG. 15, the lower portion of the silicon germanium layer 20 can be maintained as silicon germanium and a germanium layer 30 and a silicon oxide film 40 can be formed in the upper portion only. Especially, it is preferable that the active region 30 is formed of a 100% or near 100% condensed germanium layer by the oxidation process.

[0064] Next, a gate 50 may be wrapped around the silicon oxide film 40 in a fourth step. At this time, the gate 50, as shown in FIGS. 3 and 16, can be just wrapped around the silicon oxide film 40 or, as shown in FIG. 12, after forming a trench 44 and a thin gate insulating film 42, the gate 50 can be formed by filling the trench 44 with a conductive material as shown in FIG. 13.

[0065] Before forming the gate 50 in the fourth step, in order to fabricate the transistor shown in FIG. 1, a process for forming source and drain contact regions (not shown) on the germanium layer 30 exposed by etching the silicon oxide film 40 at both sides of the silicon nanowire 10 can be further processed. And then source and drain electrodes 60 and 70 can be simultaneously formed on the source and drain contact regions together with the gate 50 in the fourth step.

[0066] In another embodiment forming the source and drain electrodes 60 and 70, in order to form the transistor shown in FIG. 6, the source and drain electrodes 60 and 70 can be simultaneously formed at both ends of the germanium layer 30 together with the gate 50 in the fourth step.

[0067] In another embodiment forming the source and drain electrodes 60 and 70, in order to form the transistor shown in FIG. 14, after forming the gate 50, the fourth step can further process an ion implantation process, as shown in FIGS. 5, 14 and 16, to form source and drain regions 62 and 72 at both ends of the active region 30 and 30 and to form source and drain electrodes 60 and 70 on the source and drain regions 62 and 72, respectively.

[0068] In each embodiment described above, the active region 30 and 30, the silicon oxide film 42 and the gate 50 can be formed to be coaxially and cylindrically wrapped around the silicon nanowire 10 as a core region, respectively.

[0069] This work was supported by the National Research Foundation of Korea (NRF) funded by Ministry of Science, ICT & Future Planning (NRF-2014R1A1A1003644).