A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: forming a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

A semiconductor device is provided, comprising a substrate with a first insulating film formed thereon, and a transistor formed on the first insulating film. The transistor at least comprises an oxide semiconductor layer formed on the first insulating film, a first gate insulation film formed on the oxide semiconductor layer, a gate electrode formed above the first gate insulation film, and spacers formed on the oxide semiconductor layer. The spacers at least cover the sidewalls of the first gate insulation film and the sidewalls of the gate electrode. The gate electrode has a gate width and the first gate insulation film has a first width, wherein the gate width is different from the first width.

In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

A semiconductor device is provided, comprising a substrate with a first insulating film formed thereon, and a transistor formed on the first insulating film. The transistor at least comprises an oxide semiconductor layer formed on the first insulating film, a first gate insulation film formed on the oxide semiconductor layer, a gate electrode formed above the first gate insulation film, and spacers formed on the oxide semiconductor layer. The spacers at least cover the sidewalls of the first gate insulation film and the sidewalls of the gate electrode. The gate electrode has a gate width and the first gate insulation film has a first width, wherein the gate width is different from the first width.

A first oxide semiconductor region serving as a channel region of a TFT is formed on a first insulating region of a gate insulating film whose hydrogen content is comparatively low, and a second oxide semiconductor region that contacts with a source electrode and a drain electrode is formed on a second insulating region of a gate insulating film whose hydrogen content is comparatively high. For this reason, sheet resistance R1 of the first oxide semiconductor region is comparatively high, and sheet resistance R3 of the second oxide semiconductor region is comparatively low so that R1>R3.

The present inventive concept relates to a display device and a manufacturing method thereof. A display device according to an exemplary embodiment of the present inventive concept includes: a substrate; a first gate conductor provided on the substrate; and a gate insulator provided on the first gate conductors, wherein edges of the first gate conductor are recessed from edges of the first gate insulator, and the edges of the first gate insulator are respectively parallel with the edges of the first gate conductor.

Techniques and mechanisms for providing gate dielectric structures of a transistor. In an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (TMD) material. The channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. A composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. The composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. In another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.

Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

Semiconductor devices and methods for forming the semiconductor devices using diffusion cap layers are provided. The semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a plurality of diffusion cap layers disposed between and separating the plurality of semiconductor layers and the gate structure. In some embodiments, the plurality of diffusion cap layers function as diffusion barriers for the plurality of semiconductor layers.