A semiconductor structure includes a first gate-all-around field effect transistor, which in turn includes an upper nanosheet and a first gate structure. The first gate structure is laterally confined by first gate spacers and surrounds the upper nanosheet. The first gate structure includes a first gate dielectric on the upper nanosheet and a u-shaped first high-k material on a lower portion of the first gate spacers and on the first gate dielectric.

One aspect of the invention relates to a field effect transistor (3) comprising: a channel region (11); a source region (12) and a drain region (13); a gate structure (14) comprising: a gate dielectric layer (14b); a gate electrode (14a) with a first work function (W.sub.1); and a lateral gate conductor (14c) disposed at least against the flank of the gate electrode (14a) located on the side of the drain region (13), the lateral gate conductor (14c) extending to the gate dielectric layer (14b) in direct contact with the gate electrode (14a) and having a second work function (W.sub.2);
the second work function (W.sub.2) being: strictly greater than the first work function (W.sub.1) when the transistor is of type p; strictly lower than the first work function (W.sub.1) when the transistor is of type n.

A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer of second dielectric material being arranged between at least part of the first overlapping portion and the first terminal, whereby at least part of the first overlapping portion of the gate terminal is separated from the first terminal by the layer of first dielectric material and the layer of second dielectric material.

A thin film transistor and a display apparatus including the thin film transistor are provided. The thin film transistor includes a first gate electrode, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, and a second gate electrode on the second gate insulating layer, wherein the active layer includes a channel portion, and the channel portion includes a first channel portion overlapping the first gate electrode and a second channel portion overlapping the second gate electrode, and wherein the first gate electrode and the second gate electrode do not overlap each other in a plan view.

A structure including a first fin-type field effect transistor (finFET) in a first semiconductor fin. The first finFET includes a channel region between a first source/drain (S/D) region and a second S/D region; and a gate all around (GAA) structure. The GAA structure includes an outer gate region over the channel region and a buried gate region under of the channel region and extending between the first S/D region and the second S/D region. The outer gate region and the buried gate region each include a gate metal layer and a gate dielectric layer. The gate dielectric layer is thicker in the buried gate region than in the outer gate region.

Disclosed is a semiconductor device comprising a substrate including first and second active patterns, first and second channel patterns on the first and second active patterns and each including first and second semiconductor patterns, first source/drain patterns connected to the first channel pattern, second source/drain patterns connected to the second channel pattern, a first inner gate electrode between neighboring first semiconductor patterns, a second inner gate electrode between neighboring second semiconductor patterns, a first inner gate spacer between the first inner gate electrode and the first source/drain pattern, and a second inner gate spacer between the second inner gate electrode and the second source/drain pattern. The first inner gate spacer has a first thickness. The second inner gate spacer has a second thickness. The first thickness is greater than the second thickness.

A method and device are provided, wherein the method includes forming a stack including nanostructure channels, interposers, and a hard mask structure by forming a source/drain opening. The method further includes forming a sacrificial gate structure on the stack, and forming a spacer layer adjacent the sacrificial gate structure. The method further includes releasing the nanostructure channels by removing the interposers, and forming a gate dielectric on the nanostructure channels and a side surface of the spacer layer. The method also includes forming a reduced gate dielectric by removing a portion of the gate dielectric from the side surface of the spacer layer, the portion being laterally adjacent to the nanostructure channels, and forming a gate metal layer on the reduced gate dielectric and exposed portions of the spacer layer.

A semiconductor device including a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer in contact with the first conductive layer and the second conductive layer, a third conductive layer over the first insulating layer, a semiconductor layer in contact with the third conductive layer, the first conductive layer, and the first insulating layer, a second insulating layer over the first insulating layer, the semiconductor layer, and the third conductive layer, and a fourth conductive layer over the second insulating layer is provided. A shortest distance from a top surface of the first conductive layer to a top surface of the second conductive layer is longer than a shortest distance from the top surface of the first conductive layer to a bottom surface of the fourth conductive layer.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

A semiconductor device includes: a gate structure having a side in a first direction and extending in a second direction intersecting the first direction; a source/drain region on the side of the gate structure; a plurality of channel layers spaced apart from each other in a third direction intersecting the first direction and the second direction and surrounded by the gate structure; and a plurality of inner spacers between the gate structure and the source/drain region, wherein the plurality of inner spacers have respective heights in the third direction increasing in the third direction toward bottom, and have respective thicknesses in the first direction decreasing in the third direction toward bottom.