The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

A semiconductor device is provided in some embodiments of the present disclosure, including: a substrate, a plurality of first conductive type doped regions, a plurality of second conductive type doped regions and a conductive contact. The plurality of first conductive type doped regions are disposed in the substrate. The plurality of second conductive type doped regions are disposed in the substrate. The conductive contact is disposed in the substrate, in which the first conductive type doped regions are between the conductive contact and the plurality of second conductive type doped regions. A method of manufacturing a semiconductor device is further provided in some embodiments of the present disclosure.

A semiconductor device includes a substrate, a first well region of the first conductivity type, and a second well region of the second conductivity type. The semiconductor device also includes a drain region, a source region, and a gate structure. The drain region of the first conductivity type is formed in the first well region and the source region of the first conductivity type is formed in the second well region. The gate structure on the substrate includes the first gate stack near the source region and the second gate stack near the drain region. The first gate stack includes the first gate dielectric layer and the first gate electrode layer. The second gate stack includes the second gate dielectric layer and the second gate electrode layer. The thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

The present invention provides a high-side switch device having split gates. The high-side switch device includes: at least one tie-gate high-side switch device, each having a split gate independently connected to a gate; and at least one tie-source high-side switch device, each having a split gate independently connected to a source. The at least one tie-gate high-side switch device and the at least one tie-source high-side switch device are electrically connected in parallel. The quantity ratio of the at least one tie-gate high-side switch device to the at least one tie-source high-side switch device can be adjusted to modulate the Miller capacitance of the high-side switch device having split gates.

A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, and a gate conductive structure over the gate dielectric layer. The gate conductive structure includes a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer, and a top surface of the second metal layer is higher than a top surface of the first metal layer.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes: a substrate, a dielectric layer, a first gate structure and a second gate structure. The substrate includes discrete semiconductors arranged at a top of the substrate and extending in a vertical direction. The first gate structure is arranged in a first region of the semiconductor pillar and surrounds the semiconductor pillar. The second gate structure is arranged in a second region of the semiconductor pillar and includes a ring structure and at least one bridge structure. The ring structure surrounds the semiconductor pillar, and the at least one bridge structure penetrates through the semiconductor pillar and extends to an inner wall of the ring structure in a penetrating direction. The dielectric layer is located between the first gate structure and the semiconductor pillar, and between the second gate structure and the semiconductor pillar.

Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source/drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source/drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source/drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.

The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control region the effective doping dose has a higher value than at other points of the substrate doping increase region (2) below the gate electrode.

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

A semiconductor device structure and methods of forming the same are described. The structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.