Provided is an RF switch device and a manufacturing method thereof and, more particularly, an RF switch device and a manufacturing method thereof that improve breakdown voltage characteristics and prevent an increase in the figure of merit (FoM) value, which has a trade-off relationship with the breakdown voltage characteristics, by decreasing the path along which holes move in a body region to a body contact by including a first (gate) electrode extending along a first direction between opposite ends of a second (gate) electrode extending in a second (orthogonal) direction.

Present disclosure provides a transistor structure, including a substrate, a first gate extending along a longitudinal direction over the substrate, the first gate including a gate electrode, a second gate over the substrate and apart from the first gate, a source region of a first conductivity type in the substrate, aligning to an edge in proximity to a side of the first gate, a P-type well surrounding the source region, a drain region of the first conductivity type in the substrate, an N-type well surrounding the drain region, the second gate is entirely within a vertical projection area of the N-type well and a bottom surface of the P-type well and a bottom surface of the N-type well are substantially at a same depth from the first gate.

A metal oxide semiconductor field effect transistor (MOSFET) power device with multi gates connection includes a first-conductive type substrate, a first-conductive type epitaxial layer arranged on the first-conductive type substrate, a plurality of device trenches defined on an upper face of the first-conductive type epitaxial layer. Each of the device trenches has, from bottom of the trench to top of the trench, a bottom gate, a split gate and a trench gate. A bottom insulating layer is formed between the bottom gate and the bottom of the trench, an intermediate insulating layer is formed between the bottom gate and the split gate, an upper insulating layer is formed between the split gate and the trench gate.

A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.