Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

The embodiments described above provide mechanisms of forming contact structures with low resistance. A strained material stack with multiple sub-layers is used to lower the Schottky barrier height (SBH) of the conductive layers underneath the contact structures. The strained material stack includes a SiGe main layer, a graded SiG layer, a GeB layer, a Ge layer, and a SiGe top layer. The GeB layer moves the Schottky barrier to an interface between GeB and a metal germanide, which greatly reduces the Schottky barrier height (SBH). The lower SBH, the Ge in the SiGe top layer forms metal germanide and high B concentration in the GeB layer help to reduce the resistance of the conductive layers underneath the contact structures.

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.

Example embodiments relate to semiconductor processing methods and semiconductor components obtainable by applying the semiconductor processing methods. One example method includes providing a substrate formed of a first semiconductor material. The method also includes providing a mesa structure on the substrate and in direct contact with the substrate. The mesa structure is isolated on all lateral sides by dielectric material. Active layers of a semiconductor device are integrated in an upper portion of the mesa structure. Additionally, the method includes producing one or more openings through the dielectric material. Further, the method includes forming a cavity by removing a bottom portion of the mesa structure through the one or more openings or removing the dielectric material in a region directly adjacent to the bottom portion of the mesa structure. In addition, the method includes obtaining a thermally conductive volume by filling the cavity with a material of high thermal conductivity.

A compound transistor comprises a plurality of electrodes, a first semiconductor structure, and a second semiconductor structure. The electrodes include a source, a gate, and a drain of a first transistor. The first semiconductor structure is electrically connected to the plurality of electrodes and includes a barrier layer and a first channel layer. The second semiconductor structure includes a second channel layer, a buffer layer, and a substrate layer arranged such that the buffer layer is sandwiched between the second channel layer and the substrate layer. The second transistor structure supports the first semiconductor structure such that a connecting layer is arranged between the first and the second semiconductor structures. A source electrode is electrically connected to the second channel layer such that the source of the first transistor forms a base of a second transistor, and the source electrode forms a collector of the second transistor.

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an emitter, a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section, and an intrinsic base disposed in a second direction between the emitter and the third section of the collector. The structure further comprises a stress layer including a section positioned to overlap with the emitter, the intrinsic base, and the collector. The section of the stress layer is surrounded by a perimeter, and the first and second sections of the collector are each positioned adjacent to the perimeter of the stress layer.

A semiconductor device, such as a heterojunction bipolar transistor (HBT), having a monocrystalline extrinsic base region may be formed via a method including steps of providing a substrate that includes a dielectric isolation region and a collector region that includes semiconductor material, forming a polycrystalline semiconductor layer over the substrate, forming a monocrystalline intrinsic base layer via epitaxial growth, where the intrinsic base layer is in direct contact with the polycrystalline semiconductor layer, removing the polycrystalline semiconductor layer after forming the monocrystalline intrinsic base layer, and forming a monocrystalline extrinsic base layer via epitaxial growth, where the monocrystalline extrinsic base layer is in direct contact with the monocrystalline intrinsic base layer.

Aspects disclosed in the detailed description include an impure Indium Phosphide (InP) semiconductor substrate. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a semiconductor substrate comprising a silicon layer and an impure InP layer adjacent to the silicon layer. The impure InP layer may be epitaxially grown on a Silicon (Si) nanoridge base or directly bonded to the silicon layer after being epitaxially grown and cleaved. Utilizing an impure InP layer advantageously provides structural strength to be deployed in a 300 millimeter wafer process while achieving the electrical and thermal characteristic of InP it provides in a semiconductor substrate.