An ESD protection device includes a zener diode, and a series circuit of diodes and a series circuit of diodes that are connected in parallel with the zener diode. At the connection point between the diodes, an Al electrode film is formed on the surface of a Si substrate, and at the connection point between diodes, an Al electrode film is formed on the surface of the Si substrate. The diodes are formed on the surface of the Si substrate, and the diodes are formed in the thickness direction of the Si substrate. The Si substrate has a longitudinal direction and a shorter direction orthogonal to the longitudinal direction in planar view, and the Al electrode films are formed respectively at both ends in the shorter direction of the Si substrate. Thus, provided is an ESD protection device which suppresses the ESL, and keeps the clamp voltage low.

A diffusion diode including a p.sup.+ diffusion region, a p-type diffusion region, and an n.sup.+ diffusion region is formed in the front surface of a semiconductor substrate. A polysilicon diode including a p.sup.+ layer and an n.sup.+ layer is formed on top of a local insulating film formed on the front surface of the semiconductor substrate and faces the diffusion diode in the depth direction. The diffusion diode and the polysilicon diode are reverse-connected by electrically connecting the n.sup.+ diffusion region to the n.sup.+ layer, thereby forming a lateral protection device. The p.sup.+ layer and p.sup.+ diffusion region are respectively electrically connected to a high voltage first terminal and a low voltage second terminal of the lateral protection device. The polysilicon diode blocks a forward current generated in the diffusion diode when the electric potential of the first terminal becomes lower than the electric potential of the second terminal.

An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated.

There is provided an electronic device including at least two diodes each having a mesa structure, including: a first and a second doped semiconductor portion forming a p-n junction, such that a first part of the second doped semiconductor portion located between a second part of the second doped semiconductor portion and the first doped semiconductor portion forms an offset from the second part; a first electrode electrically connected to the first portion, and a second electrode electrically connected to the second portion at an upper face of the second part; and dielectric portions covering side faces of the first portion, the second portion, and the first electrode, wherein upper faces of the first electrode, the second electrode, and the dielectric portions form an approximately plane continuous surface.

Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.

A semiconductor device includes a first electrode, a first semiconductor layer of a first dopant type on the first electrode. A first region of the semiconductor device includes a second semiconductor layer of the second dopant type on the first semiconductor layer, a third semiconductor layer of the first dopant type on the second semiconductor layer, and a second electrode extending though the second and third semiconductor layers and inwardly of the first semiconductor layer. A second region of the semiconductor device includes an insulating layer over the first semiconductor layer, a fourth semiconductor layer of the first or second dopant type on the insulating layer, a fifth semiconductor layer of a different dopant type on the insulating layer and surrounding the fourth semiconductor layer, and a sixth semiconductor layer of the same dopant type on the insulation layer and surrounding the fifth semiconductor layer.

A chip resistor includes a substrate, and a plurality of resistor elements each having a resistive film provided on the substrate and an interconnection film provided on the resistive film in contact with the resistive film. An electrode is provided on the substrate. Fuses disconnectably connect the resistor elements to the electrode. The resistive film is made of at least one material selected from the group of NiCr, NiCrAl, NiCrSi, NiCrSiAl, TaN, TaSiO.sub.2, TiN, TiNO and TiSiON.

Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, each of the one or more diodes may be coupled with a voltage domain. One or more test pins may be coupled with one or more diodes. The test pins may be configured to be coupled to a tester. The one or more diodes may be positioned on one or more internal analog nodes to detect the presence of one or more analog faults. The one or more diodes may be configured to remain inactive during regular operation of the integrated circuit.

A diffusion diode including a p.sup.+ diffusion region, a p-type diffusion region, and an n.sup.+ diffusion region is formed in the front surface of a semiconductor substrate. A polysilicon diode including a p.sup.+ layer and an n.sup.+ layer is formed on top of a local insulating film formed on the front surface of the semiconductor substrate and faces the diffusion diode in the depth direction. The diffusion diode and the polysilicon diode are reverse-connected by electrically connecting the n.sup.+ diffusion region to the n.sup.+ layer, thereby forming a lateral protection device. The p.sup.+ layer and p.sup.+ diffusion region are respectively electrically connected to a high voltage first terminal and a low voltage second terminal of the lateral protection device. The polysilicon diode blocks a forward current generated in the diffusion diode when the electric potential of the first terminal becomes lower than the electric potential of the second terminal.

There is provided a semiconductor device capable of suppressing generation of leakage current of a diode, by applying a voltage to a gate of a gated junction diode (GJD). The semiconductor device includes an internal circuit connected with an input-output terminal, and an electrostatic discharge (ESD) protection circuit configured to protect the internal circuit from ESD, the ESD protection circuit including a first diode, wherein the first diode includes a first gate which is formed on a substrate and to which a first recovery voltage is applied, a first well of a first conductivity type which is formed within the substrate and under the first gate, a first impurity region of the first conductivity type which is formed on one side of the first gate and within the first well and is higher in doping concentration than that of the first well, and a second impurity region of a second conductivity type which is formed on other side of the first gate and within the first well.