The present invention discloses a GaN HEMT transistor with impact energy release capability for use in aerospace irradiation environment and preparation method thereof. The transistor includes a substrate layer, a gallium nitride layer, a barrier layer, and a gate structure successively arranged from bottom to top. The gallium nitride layers on both sides of the barrier layer are respectively provided with a source electrode and a drain electrode on the top surface. The gate structure is located near the source electrode and includes a p-type gallium nitride layer, a dielectric layer, an Ohmic metal pillar, and a Schottky metal layer. The present invention solves the breakdown problem caused by the inability to release impact energy during the switching process by introducing an asymmetric multi-integrated gate structure.

A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the barrier layer.

Described is a GaN fabrication process using titanium nitride (TiN) and tungsten (W) metallization optimized for high-temperature operation. An aluminum-free gate stack and backend process are disclosed. Ohmic contacts may be formed by a highly doped N+ GaN layer enabling low contact resistance with titanium nitride (TiN) and tungsten (W) metals. The gate metal thickness may be increased to counteract the higher resistivity of tungsten (W) compared to aluminum (Al). The resulting process uses only high melting point materials and is compatible with silicon carbide (SiC) or sapphire substrates for robust high-temperature GaN device performance.

A high electron mobility transistor (HEMT) includes an active region, in which a channel is formed, and a field region surrounding the active region. The HEMT may include a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; and a gate on the barrier layer. The gate may protrude from the active region to the field region on the barrier layer. The gate may include a first gate and a second gate. The first gate may be in the active region and the second gate may be in the boundary region between the active region and the field region. A work function of the second gate may be different from a work function of the first gate.

A high electron mobility transistor (HEMT) is provided in the present invention, including an AlGaN layer on a GaN substrate, a gate comprised of a first p-GaN layer on the AlGaN layer, an etch stop layer on the first p-GaN layer, a second p-GaN layer on the etch stop layer and an electrode layer on the second p-GaN layer, and a source and a drain respectively on the AlGaN layer at two sides of the gate in a first direction, wherein a width of the first p-GaN layer in the first direction is larger than a width of the second p-GaN layer in the first direction, so that the first p-GaN layer is provided with a ledge part protruding in the first direction.

A bandgap tuneable p-GaN high electron mobility transistor (HEMT) having a structure stacked on a silicon carbide substrate. The device incorporates an indium nitride nucleation layer, followed by an aluminum nitride nucleation layer, and a first aluminum gallium nitride buffer layer. A gallium nitride channel layer is deposited on this stack, with an aluminum source and a drain contact at either end. The bandgap tuneable p-GaN HEMT includes a two-dimensional molybdenum disulfide layer over the channel, covered by a second AlGaN buffer layer. A p-type gallium nitride cap layer and a platinum gate contact complete the structure. This configuration facilitates bandgap tuning and strain engineering, enhancing electron mobility and density in the two-dimensional electron gas region, making it suitable for high-power and high-frequency applications.

In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.

A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

A semiconductor device, such as a GaN-based high electron mobility transistor (HEMT), includes a hybrid drain contact structure over a channel layer and a barrier layer. The hybrid drain contact structure includes a first drain contact electrically coupled to the channel layer, a semiconductor layer over the barrier layer and including a first semiconductor portion and a second semiconductor portion, and a second drain contact on the semiconductor layer and electrically coupled to the first drain contact. The second drain contact includes a first metal portion and a second metal portion. The first metal portion and the first semiconductor portion form a first junction having a first energy barrier height. The second metal portion and the second semiconductor portion form a second junction having a second energy barrier height lower than the first energy barrier height.

A semiconductor device includes a dual-stage Schottky barrier. The dual-stage Schottky barrier includes a first stage and a second stage. The first stage is formed over a substrate stack and includes an upper layer having a length corresponding to a gate length for the device. The second stage is formed at least partially over the first stage and includes a contact segment having a length less than the gate length.