A high electron mobility transistor device including a channel layer, a first barrier layer, a gate structure, and a spacer is provided. The first barrier layer is disposed on the channel layer. The gate structure is disposed on the first barrier layer. The gate structure includes a first P-type gallium nitride layer, a second barrier layer, and a second P-type gallium nitride layer. The first P-type gallium nitride layer is disposed on the first barrier layer. The second barrier layer is disposed on the first P-type gallium nitride layer. The second P-type gallium nitride layer is disposed on the second barrier layer. A width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer. The spacer is disposed on a sidewall of the second P-type gallium nitride layer.

A nitride semiconductor device includes an electron transit layer, an electron supply layer that is formed on the electron transit layer, a gate layer that is formed on the electron supply layer and contains an Al.sub.1-XGa.sub.XN (0<X<1) based material containing a first impurity, a gate electrode that is formed on the gate layer and is in Schottky junction with the gate layer, and a source electrode and a drain electrode that are electrically connected to the electron supply layer. By this arrangement, a gate withstand voltage can be improved and therefore, a nitride semiconductor device of high reliability can be provided.

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a source and a drain over a substrate. A gate is over the substrate and laterally between the source and the drain. A cap structure includes a horizontally extending segment and a vertically extending segment protruding outward from a lower surface of the horizontally extending segment. The vertically extending segment and the horizontally extending segment are laterally between the source and the gate.

A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

Disclosed herein are a field effect transistor and a preparation method therefor, and a memory and a display. The field effect transistor comprises: a first source/drain layer (1), an insulating layer (2) and a second source/drain layer (3), which are sequentially stacked; and a gate electrode (5) and a channel layer (4), which surrounds the gate electrode (5), wherein the gate electrode (5) and the channel layer (4) are located in the second source/drain layer (3) and the insulating layer (2), and the channel layer (4) is in contact with the first source/drain layer (1) and the second source/drain layer (3). The channel layer (4) comprises an outer layer and an inner layer (42), wherein the inner layer (42) is close to the gate electrode (5); the outer layer is in contact with the insulating layer (2), the first source/drain layer (1) and the second source/drain layer (3); and both the outer layer and the inner layer (42) are made of indium oxide. Since both the outer layer and the inner layer (42) of the channel layer (4) in the field effect transistor are made of indium oxide, the problems of further reducing the size of the transistor, reducing the power consumption and improving the contact performance can be solved.

A semiconductor structure includes a substrate, a channel layer and a barrier layer stacked sequentially, and a P-type semiconductor layer in a gate region is configured to implement an enhancement mode device; a crystalline layer, a SiN layer and an amorphous layer stacked sequentially on the P-type semiconductor layer, where the crystalline layer forms a junction with the P-type semiconductor layer, so that injection of carriers is blocked, and leakage current is reduced. The crystalline layer enhances polarization, a hole concentration of the P-type semiconductor layer is induced to increase, and a threshold voltage of the device is improved. In addition, when a voltage is applied to the gate, a uniform electric field distribution may be formed in the gate region, and a probability that the device is broken down is reduced. The amorphous layer may reduce leakage.

A transistor device includes a substrate and a gate structure. The gate structure is disposed on the substrate. The gate structure includes a first metal layer and a refractory metal layer disposed on the first metal layer, wherein the first metal layer is disconnected and the refractory metal layer is disconnected.

The present disclosure discloses a semiconductor device comprising a plurality of epitaxial layers including a barrier layer and a channel layer such that two-dimensional carrier densities are formed at an interface of the barrier layer and the channel layer, wherein a priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer can be changed by applying an electric field across the barrier layer. The semiconductor device further comprises a first source terminal and a second source terminal, wherein in one of the first source terminal and the second source terminal is ohmic to electrons and other one is ohmic to holes. The semiconductor device further comprises a first drain terminal and a second drain terminal, a gate terminal, and a set terminal ohmic to the channel layer.

This normally-off mode polarization super junction GaN-based field effect transistor has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12 (0<x<1), an island-like undoped GaN layer 13, a p-type GaN layer 14, a p-type In.sub.yGa.sub.1-yN layer 15 (0<y<1), a gate electrode 16 on the p-type In.sub.yGa.sub.1-yN layer 15 and a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12. When the polarization charge amount of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 is denoted as N.sub.PZ and the thickness of the Al.sub.xGa.sub.1-xN layer 12 is denoted as d, N.sub.PZ d2.6410.sup.14 [cm.sup.2 nm] is satisfied.

A transistor having a GaN stack on a substrate, an AlGaN barrier layer on the GaN stack, a gate stack including a p-GaN layer on the AlGaN barrier layer, a dielectric layer on a first portion of the p-GaN layer, and a gate electrode on the dielectric layer, and an AlGaN cap layer on a second portion of the p-GaN layer and laterally outward of a portion of the gate electrode. A method of fabricating a semiconductor device includes forming a dielectric layer on a patterned p-GaN layer and forming a gate electrode on the dielectric layer.